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PCI driver rewrite

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This commit is contained in:
Kamil Kowalczyk
2025-11-23 21:37:12 +01:00
parent e105b2fe35
commit fa152cac4d
9 changed files with 267 additions and 505 deletions
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136
kernel/pci/pci.h
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@ -4,86 +4,68 @@
#include <stdint.h>
#include <stddef.h>
#define PCI_MAKE_ID(bus, dev, fn) (((bus)<<16) | ((dev)<<11) | ((fn)<<8))
#define PCI_CONFIG_ADDR 0xCF8
#define PCI_CONFIG_DATA 0xCFC
#define PCI_MULTIFN 0x80
#define PCI_GENERIC 0x00
#define PCI_PCI_BRIDGE 0x01
#define PCI_CARDBUS_BRIDGE 0x02
#define PCI_VENDORID 0x00
#define PCI_DEVICEID 0x02
#define PCI_CMD 0x04
#define PCI_STATUS 0x06
#define PCI_REVID 0x08
#define PCI_PROGINTF 0x09
#define PCI_SUBCLASS 0x0A
#define PCI_CLASSCODE 0x0B
#define PCI_CACHELINESZ 0x0C
#define PCI_LATENCY 0x0D
#define PCI_HDRTYPE 0x0E
#define PCI_BIST 0x0F
#define PCI_BAR0 0x10
#define PCI_BAR1 0x14
#define PCI_BAR2 0x18
#define PCI_BAR3 0x1C
#define PCI_BAR4 0x20
#define PCI_BAR5 0x24
#define PCI_CARBUS_CIS 0x28
#define PCI_SUBSYS_VENDORID 0x2C
#define PCI_SUBSYS_DEVICEID 0x2E
#define PCI_EXPROM 0x30
#define PCI_CAP 0x34
#define PCI_INTRLINE 0x3C
#define PCI_INTRPIN 0x3D
#define PCI_MIN_GRANT 0x3E
#define PCI_MAX_LATENCY 0x3F
#define PCI_BAR_IO 0x01
#define PCI_BAR_MEM32 0x02
#define PCI_BAR_MEM64 0x04
#define PCI_BAR_PREFETCH 0x08
typedef struct {
union { void *addr; uint16_t port; } u;
uint64_t size;
uint32_t flags;
} PciBar;
typedef struct {
uint16_t vendorid;
uint16_t deviceid;
uint8_t classcode;
uint8_t subclass;
uint8_t progintf;
uint32_t bus, dev, fn;
} PciDevInfo;
typedef struct {
uint16_t k1;
uint16_t k2;
void (*initfn)(PciDevInfo *info);
} PciMatch;
#define PCI_DEV_MAGIC 0xAB0BA
typedef struct {
PciDevInfo devinfo;
typedef union {
uint32_t bits;
struct {
uint32_t alwayszero: 2;
uint32_t fieldnum: 6;
uint32_t fnnum: 3;
uint32_t devnum: 5;
uint32_t busnum: 8;
uint32_t resv: 7;
uint32_t enable: 1;
};
} PciDev;
uint8_t pci_read8(uint32_t id, uint32_t reg);
uint16_t pci_read16(uint32_t id, uint32_t reg);
uint32_t pci_read32(uint32_t id, uint32_t reg);
void pci_write8(uint32_t id, uint32_t reg, uint8_t v);
void pci_write16(uint32_t id, uint32_t reg, uint16_t v);
void pci_write32(uint32_t id, uint32_t reg, uint32_t v);
void pci_getbar(PciBar *bar, uint32_t id, uint32_t idx);
#define PCI_CFG_ADDR 0xCF8
#define PCI_CFG_DATA 0xCFC
#define PCI_VENDORID 0x00
#define PCI_DEVICEID 0x02
#define PCI_CMD 0x04
#define PCI_STATUS 0x06
#define PCI_REVID 0x08
#define PCI_PROGIF 0x09
#define PCI_SUBCLASS 0x0A
#define PCI_CLASS 0x0B
#define PCI_CACHELINESZ 0x0C
#define PCI_LTNCY_TIMER 0x0D
#define PCI_HDRTYPE 0x0E
#define PCI_BIST 0x0F
#define PCI_BAR0 0x10
#define PCI_BAR1 0x14
#define PCI_BAR2 0x18
#define PCI_BAR3 0x1C
#define PCI_BAR4 0x20
#define PCI_BAR5 0x24
#define PCI_INTRLINE 0x3C
#define PCI_SCNDRY_BUS 0x09
#define PCI_HDR_DEV 0
#define PCI_HDR_BRIDGE 1
#define PCI_HDR_CARDBUS 2
#define PCI_DEV_PER_BUS 32
#define PCI_FN_PER_DEV 32
uint32_t pci_read(PciDev dev, uint32_t field);
void pci_write(PciDev dev, uint32_t field, uint32_t v);
uint32_t pci_devtype(PciDev dev);
uint32_t pci_scndrybus(PciDev dev);
uint32_t pci_isend(PciDev dev);
PciDev pci_scanfn(uint16_t vendorid, uint16_t deviceid, uint32_t bus,
uint32_t device, uint32_t fn, int devtype);
PciDev pci_scanbus(uint16_t vendorid, uint16_t deviceid,
uint32_t bus, int devtype);
PciDev pci_scandev(uint16_t vendorid, uint16_t deviceid,
uint32_t bus, uint32_t device, int devtype);
PciDev pci_getdev(uint16_t vendorid, uint16_t deviceid, int devtype);
void pci_init(void);
#define PCI_INIT_ARRAY_MAX 0x100
typedef void (*PciInitFn)(void);
extern PciInitFn PCI_INIT_ARRAY[PCI_INIT_ARRAY_MAX];
#endif // PCI_PCI_H_