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PCI driver rewrite

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This commit is contained in:
Kamil Kowalczyk
2025-11-23 21:37:12 +01:00
parent e105b2fe35
commit fa152cac4d
9 changed files with 267 additions and 505 deletions
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52
kernel/pci/ata.c Normal file
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#include <stdint.h>
#include <stddef.h>
#include "pci/pci.h"
#include "storedev/storedev.h"
#include "storedev/atasd.h"
#include "kprintf.h"
#define ATA_PROBE(STRING, IOBASE, CTRLBASE, S_OR_M) \
ps = ata_probesize_bytes((IOBASE), (CTRLBASE), (S_OR_M)); \
if (ps > 0) { \
AtaSdInitExtra extra = { \
.devno = (S_OR_M), \
.capacity = ps, \
.iobase = (IOBASE), \
.ctrlbase = (CTRLBASE), \
}; \
storedev_create(STOREDEV_ATASD, (STRING), (void *)&extra); \
}
#define ATA_MASTER 0x00
#define ATA_SLAVE 0x01
#define ATA_PRIM_IO 0x1F0
#define ATA_PRIM_CTRL 0x3F6
#define ATA_SCND_IO 0x170
#define ATA_SCND_CTRL 0x376
void pci_ata_init(void) {
PciDev dev = pci_getdev(0x8086, 0x7010, -1);
uint16_t iobase, ctrlbase;
uint64_t ps;
uint32_t bar0 = pci_read(dev, PCI_BAR0);
uint32_t bar1 = pci_read(dev, PCI_BAR1);
uint32_t bar2 = pci_read(dev, PCI_BAR2);
uint32_t bar3 = pci_read(dev, PCI_BAR3);
LOG("pci", "ATA bar0=0x%x, bar1=0x%x, bar2=0x%x, bar3=0x%x\n", bar0, bar1, bar2, bar3);
iobase = (bar0 & 0xFFFFFFFC) + ATA_PRIM_IO * (!bar0);
ctrlbase = (bar1 & 0xFFFFFFFC) + ATA_PRIM_CTRL * (!bar1);
LOG("pci", "ATA CHANNEL PRIM: iobase=0x%x, ctrlbase=0x%x\n", iobase, ctrlbase);
ATA_PROBE("atasd0m", iobase, ctrlbase, ATA_MASTER);
ATA_PROBE("atasd0s", iobase, ctrlbase, ATA_SLAVE);
iobase = (bar2 & 0xFFFFFFFC) + ATA_SCND_IO * (!bar2);
ctrlbase = (bar3 & 0xFFFFFFFC) + ATA_SCND_CTRL * (!bar3);
LOG("pci", "ATA CHANNEL SCND: iobase=0x%x, ctrlbase=0x%x\n", iobase, ctrlbase);
ATA_PROBE("atasd1m", iobase, ctrlbase, ATA_MASTER);
ATA_PROBE("atasd2s", iobase, ctrlbase, ATA_SLAVE);
}

6
kernel/pci/ata.h Normal file
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#ifndef PCI_ATA_H_
#define PCI_ATA_H_
void pci_ata_init(void);
#endif // PCI_ATA_H_

44
kernel/pci/ide.c
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#include <stdint.h>
#include <stddef.h>
#include "pci/pci.h"
#include "pci/ide.h"
#include "storedev/atasd.h"
#include "storedev/storedev.h"
#include "util/util.h"
#include "kprintf.h"
#define ATA_MASTER 0x00
#define ATA_SLAVE 0x01
#define ATA_PROBE(STRING, IOBASE, CTRLBASE, S_OR_M) \
ps = ata_probesize_bytes((IOBASE), (CTRLBASE), (S_OR_M)); \
if (ps > 0) { \
AtaSdInitExtra extra = { \
.devno = (S_OR_M), \
.capacity = ps, \
.iobase = (IOBASE), \
.ctrlbase = (CTRLBASE), \
}; \
storedev_create(STOREDEV_ATASD, (STRING), (void *)&extra); \
}
void pci_ide_init(PciDevInfo *devinfo) {
LOG("pci", "init ATA drive\n");
uint16_t iobase, ctrlbase;
uint64_t ps;
if (!(devinfo->progintf & 0x1)) {
iobase = 0x1F0;
ctrlbase = 0x3F6;
}
ATA_PROBE("atasd0m", iobase, ctrlbase, ATA_MASTER)
ATA_PROBE("atasd0s", iobase, ctrlbase, ATA_SLAVE)
if (!(devinfo->progintf & 0x4)) {
iobase = 0x170;
ctrlbase = 0x376;
}
ATA_PROBE("atasd1m", iobase, ctrlbase, ATA_MASTER)
ATA_PROBE("atasd1s", iobase, ctrlbase, ATA_SLAVE)
}

8
kernel/pci/ide.h
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#ifndef PCI_IDE_H_
#define PCI_IDE_H_
#include "pci/pci.h"
void pci_ide_init(PciDevInfo *devinfo);
#endif // PCI_IDE_H_

242
kernel/pci/pci.c
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@ -1,126 +1,182 @@
#include <stdint.h>
#include <stddef.h>
#include "pci/pci.h"
#include "pci/reg.h"
#include "pci/ata.h"
#include "io/io.h"
#include "std/string.h"
#include "util/util.h"
#include "pci/ide.h"
#include "kprintf.h"
uint8_t pci_read8(uint32_t id, uint32_t reg) {
uint32_t addr = 0x80000000 | id | (reg & 0xFC);
io_out32(PCI_CONFIG_ADDR, addr);
return io_in8(PCI_CONFIG_DATA + (reg & 0x03));
static PciDev PCI_DEV_ZERO = {0};
uint32_t PCI_SIZE_MAP[100] = {0};
uint32_t pci_read(PciDev dev, uint32_t field) {
dev.fieldnum = (field & 0xFC) >> 2;
dev.enable = 1;
io_out32(PCI_CFG_ADDR, dev.bits);
uint32_t size = PCI_SIZE_MAP[field];
uint8_t u8; uint16_t u16; uint32_t u32;
switch (size) {
case 1:
u8 = io_in8(PCI_CFG_DATA + (field & 0x3));
return (uint32_t)u8;
case 2:
u16 = io_in16(PCI_CFG_DATA + (field & 0x2));
return (uint32_t)u16;
case 4:
u32 = io_in32(PCI_CFG_DATA);
return u32;
default:
return 0xFFFF;
}
}
uint16_t pci_read16(uint32_t id, uint32_t reg) {
uint32_t addr = 0x80000000 | id | (reg & 0xFC);
io_out32(PCI_CONFIG_ADDR, addr);
return io_in16(PCI_CONFIG_DATA + (reg & 0x02));
void pci_write(PciDev dev, uint32_t field, uint32_t v) {
dev.fieldnum = (field & 0xFC) >> 2;
dev.enable = 1;
io_out32(PCI_CFG_ADDR, dev.bits);
io_out32(PCI_CFG_DATA, v);
}
uint32_t pci_read32(uint32_t id, uint32_t reg) {
uint32_t addr = 0x80000000 | id | (reg & 0xFC);
io_out32(PCI_CONFIG_ADDR, addr);
return io_in32(PCI_CONFIG_DATA + reg);
uint32_t pci_devtype(PciDev dev) {
uint32_t a = pci_read(dev, PCI_CLASS) << 8;
uint32_t b = pci_read(dev, PCI_SUBCLASS);
return a | b;
}
void pci_write8(uint32_t id, uint32_t reg, uint8_t v) {
uint32_t addr = 0x80000000 | id | (reg & 0xFC);
io_out32(PCI_CONFIG_ADDR, addr);
io_out8(PCI_CONFIG_DATA + (reg & 0x03), v);
uint32_t pci_scndrybus(PciDev dev) {
return pci_read(dev, PCI_SCNDRY_BUS);
}
void pci_write16(uint32_t id, uint32_t reg, uint16_t v) {
uint32_t addr = 0x80000000 | id | (reg & 0xFC);
io_out32(PCI_CONFIG_ADDR, addr);
io_out16(PCI_CONFIG_DATA + (reg & 0x02), v);
uint32_t pci_isend(PciDev dev) {
return !(pci_read(dev, PCI_HDRTYPE));
}
void pci_write32(uint32_t id, uint32_t reg, uint32_t v) {
uint32_t addr = 0x80000000 | id | (reg & 0xFC);
io_out32(PCI_CONFIG_ADDR, addr);
io_out32(PCI_CONFIG_DATA + reg, v);
PciDev pci_scanfn(uint16_t vendorid, uint16_t deviceid, uint32_t bus,
uint32_t device, uint32_t fn, int devtype) {
PciDev dev; memset(&dev, 0, sizeof(dev));
dev.busnum = bus;
dev.devnum = device;
dev.fnnum = fn;
// bridge
if (pci_devtype(dev) == 0x0604) {
pci_scanbus(vendorid, deviceid, pci_scndrybus(dev), devtype);
}
if (devtype == -1 || (uint32_t)devtype == pci_devtype(dev)) {
uint32_t venid = pci_read(dev, PCI_VENDORID);
uint32_t devid = pci_read(dev, PCI_DEVICEID);
if (devid == deviceid && venid == vendorid) {
return dev;
}
}
return PCI_DEV_ZERO;
}
void pci_readbar(uint32_t id, uint32_t idx, uint32_t *addr, uint32_t *mask) {
uint32_t reg = PCI_BAR0 + idx * sizeof(uint32_t);
*addr = pci_read32(id, reg);
pci_write32(id, reg, 0xffffffff);
*mask = pci_read32(id, reg);
pci_write32(id, reg, *addr);
PciDev pci_scanbus(uint16_t vendorid, uint16_t deviceid,
uint32_t bus, int devtype) {
for (uint32_t device = 0; device < PCI_DEV_PER_BUS; device++) {
PciDev d = pci_scandev(vendorid, deviceid, bus, device, devtype);
if (d.bits) {
return d;
}
}
return PCI_DEV_ZERO;
}
void pci_getbar(PciBar *bar, uint32_t id, uint32_t idx) {
uint32_t addrlo;
uint32_t masklo;
pci_readbar(id, idx, &addrlo, &masklo);
PciDev pci_scandev(uint16_t vendorid, uint16_t deviceid,
uint32_t bus, uint32_t device, int devtype) {
PciDev dev; memset(&dev, 0, sizeof(dev));
dev.busnum = bus;
dev.devnum = device;
if (addrlo & PCI_BAR_MEM32) {
bar->u.addr = (void *)((uint64_t)(addrlo & ~0x3));
bar->size = ~(masklo & ~0xF) + 1;
bar->flags = addrlo & 0xF;
} else if (addrlo & PCI_BAR_MEM64) {
uint32_t addrhi;
uint32_t maskhi;
pci_readbar(id, idx+1, &addrhi, &maskhi);
bar->u.addr = (void *)(((uint64_t)addrhi << 32) | ((uint64_t)addrlo & ~0xF));
bar->size = ~(((uint64_t)maskhi << 32) | ((uint64_t)masklo & ~0xF)) + 1;
bar->flags = addrlo & 0xF;
} else if (addrlo & PCI_BAR_IO) {
bar->u.port = (uint16_t)(addrlo & ~0x3);
bar->size = (uint16_t)(~(masklo & ~0x3) + 1);
bar->flags = addrlo & 0x3;
}
}
static PciMatch PCI_MATCHES[] = {
{ 0x8086, 0x7010, &pci_ide_init },
};
void pci_visit(uint32_t bus, uint32_t dev, uint32_t fn) {
uint32_t id = PCI_MAKE_ID(bus, dev, fn);
PciDevInfo devinfo;
memset(&devinfo, 0, sizeof(devinfo));
devinfo.vendorid = pci_read16(id, PCI_VENDORID);
if (devinfo.vendorid == 0xffff) {
return;
if (pci_read(dev, PCI_VENDORID) == 0xFFFF) {
return PCI_DEV_ZERO;
}
devinfo.deviceid = pci_read16(id, PCI_DEVICEID);
devinfo.progintf = pci_read8(id, PCI_PROGINTF);
devinfo.subclass = pci_read8(id, PCI_SUBCLASS);
devinfo.classcode = pci_read8(id, PCI_CLASSCODE);
PciDev d = pci_scanfn(vendorid, deviceid, bus, device, 0, devtype);
if (d.bits) {
return d;
}
devinfo.bus = bus;
devinfo.dev = dev;
devinfo.fn = fn;
if (pci_isend(dev)) {
return PCI_DEV_ZERO;
}
LOG("pci", "%02X:%02X:%u 0x%04X/0x%04X: %s\n",
bus, dev, fn, devinfo.vendorid, devinfo.deviceid,
pci_classname(devinfo.classcode, devinfo.subclass, devinfo.progintf));
for (size_t i = 0; i < LEN(PCI_MATCHES); i++) {
if (PCI_MATCHES[i].k1 == devinfo.vendorid && PCI_MATCHES[i].k2 == devinfo.deviceid) {
PCI_MATCHES[i].initfn(&devinfo);
for (uint32_t fn = 1; fn < PCI_FN_PER_DEV; fn++) {
if (pci_read(dev, PCI_VENDORID) != 0xFFFF) {
d = pci_scanfn(vendorid, deviceid, bus, device, fn, devtype);
if (d.bits) {
return d;
}
}
}
return PCI_DEV_ZERO;
}
PciDev pci_getdev(uint16_t vendorid, uint16_t deviceid, int devtype) {
PciDev d = pci_scanbus(vendorid, deviceid, 0, devtype);
if (d.bits) {
return d;
}
if (pci_isend(PCI_DEV_ZERO)) {
ERR("pci", "pci_getdev() failed\n");
}
for (uint32_t fn = 1; fn < PCI_FN_PER_DEV; fn++) {
PciDev d2; memset(&d2, 0, sizeof(d2));
d2.fnnum = fn;
if (pci_read(d2, PCI_VENDORID) == 0xFFFF) {
break;
}
d = pci_scanbus(vendorid, deviceid, fn, devtype);
if (d.bits) {
return d;
}
}
return PCI_DEV_ZERO;
}
void pci_init_size_map(void) {
PCI_SIZE_MAP[PCI_VENDORID] = 2;
PCI_SIZE_MAP[PCI_DEVICEID] = 2;
PCI_SIZE_MAP[PCI_CMD] = 2;
PCI_SIZE_MAP[PCI_STATUS] = 2;
PCI_SIZE_MAP[PCI_SUBCLASS] = 1;
PCI_SIZE_MAP[PCI_CLASS] = 1;
PCI_SIZE_MAP[PCI_CACHELINESZ] = 1;
PCI_SIZE_MAP[PCI_LTNCY_TIMER] = 1;
PCI_SIZE_MAP[PCI_HDRTYPE] = 1;
PCI_SIZE_MAP[PCI_BIST] = 1;
PCI_SIZE_MAP[PCI_BAR0] = 4;
PCI_SIZE_MAP[PCI_BAR1] = 4;
PCI_SIZE_MAP[PCI_BAR2] = 4;
PCI_SIZE_MAP[PCI_BAR3] = 4;
PCI_SIZE_MAP[PCI_BAR4] = 4;
PCI_SIZE_MAP[PCI_BAR5] = 4;
PCI_SIZE_MAP[PCI_INTRLINE] = 1;
PCI_SIZE_MAP[PCI_SCNDRY_BUS] = 1;
}
PciInitFn PCI_INIT_ARRAY[PCI_INIT_ARRAY_MAX] = {
&pci_ata_init,
};
void pci_init_devs(void) {
for (size_t i = 0; i < LEN(PCI_INIT_ARRAY); i++) {
if (PCI_INIT_ARRAY[i] != NULL)
PCI_INIT_ARRAY[i]();
}
}
void pci_init(void) {
for (uint32_t bus = 0; bus < 0x100; bus++) {
for (uint32_t dev = 0; dev < 32; dev++) {
uint32_t baseid = PCI_MAKE_ID(bus, dev, 0);
uint8_t hdrtype = pci_read8(baseid, PCI_HDRTYPE);
uint32_t fncount = hdrtype & PCI_MULTIFN ? 8 : 1;
for (uint32_t fn = 0; fn < fncount; fn++) {
pci_visit(bus, dev, fn);
}
}
}
pci_init_size_map();
pci_init_devs();
}

136
kernel/pci/pci.h
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@ -4,86 +4,68 @@
#include <stdint.h>
#include <stddef.h>
#define PCI_MAKE_ID(bus, dev, fn) (((bus)<<16) | ((dev)<<11) | ((fn)<<8))
#define PCI_CONFIG_ADDR 0xCF8
#define PCI_CONFIG_DATA 0xCFC
#define PCI_MULTIFN 0x80
#define PCI_GENERIC 0x00
#define PCI_PCI_BRIDGE 0x01
#define PCI_CARDBUS_BRIDGE 0x02
#define PCI_VENDORID 0x00
#define PCI_DEVICEID 0x02
#define PCI_CMD 0x04
#define PCI_STATUS 0x06
#define PCI_REVID 0x08
#define PCI_PROGINTF 0x09
#define PCI_SUBCLASS 0x0A
#define PCI_CLASSCODE 0x0B
#define PCI_CACHELINESZ 0x0C
#define PCI_LATENCY 0x0D
#define PCI_HDRTYPE 0x0E
#define PCI_BIST 0x0F
#define PCI_BAR0 0x10
#define PCI_BAR1 0x14
#define PCI_BAR2 0x18
#define PCI_BAR3 0x1C
#define PCI_BAR4 0x20
#define PCI_BAR5 0x24
#define PCI_CARBUS_CIS 0x28
#define PCI_SUBSYS_VENDORID 0x2C
#define PCI_SUBSYS_DEVICEID 0x2E
#define PCI_EXPROM 0x30
#define PCI_CAP 0x34
#define PCI_INTRLINE 0x3C
#define PCI_INTRPIN 0x3D
#define PCI_MIN_GRANT 0x3E
#define PCI_MAX_LATENCY 0x3F
#define PCI_BAR_IO 0x01
#define PCI_BAR_MEM32 0x02
#define PCI_BAR_MEM64 0x04
#define PCI_BAR_PREFETCH 0x08
typedef struct {
union { void *addr; uint16_t port; } u;
uint64_t size;
uint32_t flags;
} PciBar;
typedef struct {
uint16_t vendorid;
uint16_t deviceid;
uint8_t classcode;
uint8_t subclass;
uint8_t progintf;
uint32_t bus, dev, fn;
} PciDevInfo;
typedef struct {
uint16_t k1;
uint16_t k2;
void (*initfn)(PciDevInfo *info);
} PciMatch;
#define PCI_DEV_MAGIC 0xAB0BA
typedef struct {
PciDevInfo devinfo;
typedef union {
uint32_t bits;
struct {
uint32_t alwayszero: 2;
uint32_t fieldnum: 6;
uint32_t fnnum: 3;
uint32_t devnum: 5;
uint32_t busnum: 8;
uint32_t resv: 7;
uint32_t enable: 1;
};
} PciDev;
uint8_t pci_read8(uint32_t id, uint32_t reg);
uint16_t pci_read16(uint32_t id, uint32_t reg);
uint32_t pci_read32(uint32_t id, uint32_t reg);
void pci_write8(uint32_t id, uint32_t reg, uint8_t v);
void pci_write16(uint32_t id, uint32_t reg, uint16_t v);
void pci_write32(uint32_t id, uint32_t reg, uint32_t v);
void pci_getbar(PciBar *bar, uint32_t id, uint32_t idx);
#define PCI_CFG_ADDR 0xCF8
#define PCI_CFG_DATA 0xCFC
#define PCI_VENDORID 0x00
#define PCI_DEVICEID 0x02
#define PCI_CMD 0x04
#define PCI_STATUS 0x06
#define PCI_REVID 0x08
#define PCI_PROGIF 0x09
#define PCI_SUBCLASS 0x0A
#define PCI_CLASS 0x0B
#define PCI_CACHELINESZ 0x0C
#define PCI_LTNCY_TIMER 0x0D
#define PCI_HDRTYPE 0x0E
#define PCI_BIST 0x0F
#define PCI_BAR0 0x10
#define PCI_BAR1 0x14
#define PCI_BAR2 0x18
#define PCI_BAR3 0x1C
#define PCI_BAR4 0x20
#define PCI_BAR5 0x24
#define PCI_INTRLINE 0x3C
#define PCI_SCNDRY_BUS 0x09
#define PCI_HDR_DEV 0
#define PCI_HDR_BRIDGE 1
#define PCI_HDR_CARDBUS 2
#define PCI_DEV_PER_BUS 32
#define PCI_FN_PER_DEV 32
uint32_t pci_read(PciDev dev, uint32_t field);
void pci_write(PciDev dev, uint32_t field, uint32_t v);
uint32_t pci_devtype(PciDev dev);
uint32_t pci_scndrybus(PciDev dev);
uint32_t pci_isend(PciDev dev);
PciDev pci_scanfn(uint16_t vendorid, uint16_t deviceid, uint32_t bus,
uint32_t device, uint32_t fn, int devtype);
PciDev pci_scanbus(uint16_t vendorid, uint16_t deviceid,
uint32_t bus, int devtype);
PciDev pci_scandev(uint16_t vendorid, uint16_t deviceid,
uint32_t bus, uint32_t device, int devtype);
PciDev pci_getdev(uint16_t vendorid, uint16_t deviceid, int devtype);
void pci_init(void);
#define PCI_INIT_ARRAY_MAX 0x100
typedef void (*PciInitFn)(void);
extern PciInitFn PCI_INIT_ARRAY[PCI_INIT_ARRAY_MAX];
#endif // PCI_PCI_H_

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kernel/pci/reg.c
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#include <stdint.h>
#include <stddef.h>
#include "pci/reg.h"
const char *pci_devname(uint32_t vendorid, uint32_t deviceid) {
return "Unknown Device";
}
const char *pci_classname(uint32_t classcode, uint32_t subclass, uint32_t progintf) {
switch ((classcode << 8) | subclass)
{
case PCI_VGA_COMPATIBLE: return "VGA-Compatible Device";
case PCI_STORAGE_SCSI: return "SCSI Storage Controller";
case PCI_STORAGE_IDE: return "IDE Interface";
case PCI_STORAGE_FLOPPY: return "Floppy Disk Controller";
case PCI_STORAGE_IPI: return "IPI Bus Controller";
case PCI_STORAGE_RAID: return "RAID Bus Controller";
case PCI_STORAGE_ATA: return "ATA Controller";
case PCI_STORAGE_SATA: return "SATA Controller";
case PCI_STORAGE_OTHER: return "Mass Storage Controller";
case PCI_NETWORK_ETHERNET: return "Ethernet Controller";
case PCI_NETWORK_TOKEN_RING: return "Token Ring Controller";
case PCI_NETWORK_FDDI: return "FDDI Controller";
case PCI_NETWORK_ATM: return "ATM Controller";
case PCI_NETWORK_ISDN: return "ISDN Controller";
case PCI_NETWORK_WORLDFIP: return "WorldFip Controller";
case PCI_NETWORK_PICGMG: return "PICMG Controller";
case PCI_NETWORK_OTHER: return "Network Controller";
case PCI_DISPLAY_VGA: return "VGA-Compatible Controller";
case PCI_DISPLAY_XGA: return "XGA-Compatible Controller";
case PCI_DISPLAY_3D: return "3D Controller";
case PCI_DISPLAY_OTHER: return "Display Controller";
case PCI_MULTIMEDIA_VIDEO: return "Multimedia Video Controller";
case PCI_MULTIMEDIA_AUDIO: return "Multimedia Audio Controller";
case PCI_MULTIMEDIA_PHONE: return "Computer Telephony Device";
case PCI_MULTIMEDIA_AUDIO_DEVICE: return "Audio Device";
case PCI_MULTIMEDIA_OTHER: return "Multimedia Controller";
case PCI_MEMORY_RAM: return "RAM Memory";
case PCI_MEMORY_FLASH: return "Flash Memory";
case PCI_MEMORY_OTHER: return "Memory Controller";
case PCI_BRIDGE_HOST: return "Host Bridge";
case PCI_BRIDGE_ISA: return "ISA Bridge";
case PCI_BRIDGE_EISA: return "EISA Bridge";
case PCI_BRIDGE_MCA: return "MicroChannel Bridge";
case PCI_BRIDGE_PCI: return "PCI Bridge";
case PCI_BRIDGE_PCMCIA: return "PCMCIA Bridge";
case PCI_BRIDGE_NUBUS: return "NuBus Bridge";
case PCI_BRIDGE_CARDBUS: return "CardBus Bridge";
case PCI_BRIDGE_RACEWAY: return "RACEway Bridge";
case PCI_BRIDGE_OTHER: return "Bridge Device";
case PCI_COMM_SERIAL: return "Serial Controller";
case PCI_COMM_PARALLEL: return "Parallel Controller";
case PCI_COMM_MULTIPORT: return "Multiport Serial Controller";
case PCI_COMM_MODEM: return "Modem";
case PCI_COMM_OTHER: return "Communication Controller";
case PCI_SYSTEM_PIC: return "PIC";
case PCI_SYSTEM_DMA: return "DMA Controller";
case PCI_SYSTEM_TIMER: return "Timer";
case PCI_SYSTEM_RTC: return "RTC";
case PCI_SYSTEM_PCI_HOTPLUG: return "PCI Hot-Plug Controller";
case PCI_SYSTEM_SD: return "SD Host Controller";
case PCI_SYSTEM_OTHER: return "System Peripheral";
case PCI_INPUT_KEYBOARD: return "Keyboard Controller";
case PCI_INPUT_PEN: return "Pen Controller";
case PCI_INPUT_MOUSE: return "Mouse Controller";
case PCI_INPUT_SCANNER: return "Scanner Controller";
case PCI_INPUT_GAMEPORT: return "Gameport Controller";
case PCI_INPUT_OTHER: return "Input Controller";
case PCI_DOCKING_GENERIC: return "Generic Docking Station";
case PCI_DOCKING_OTHER: return "Docking Station";
case PCI_PROCESSOR_386: return "386";
case PCI_PROCESSOR_486: return "486";
case PCI_PROCESSOR_PENTIUM: return "Pentium";
case PCI_PROCESSOR_ALPHA: return "Alpha";
case PCI_PROCESSOR_MIPS: return "MIPS";
case PCI_PROCESSOR_CO: return "CO-Processor";
case PCI_SERIAL_FIREWIRE: return "FireWire (IEEE 1394)";
case PCI_SERIAL_SSA: return "SSA";
case PCI_SERIAL_USB:
switch (progintf)
{
case PCI_SERIAL_USB_UHCI: return "USB (UHCI)";
case PCI_SERIAL_USB_OHCI: return "USB (OHCI)";
case PCI_SERIAL_USB_EHCI: return "USB2";
case PCI_SERIAL_USB_XHCI: return "USB3";
case PCI_SERIAL_USB_OTHER: return "USB Controller";
default: return "Unknown USB Class";
}
break;
case PCI_SERIAL_FIBER: return "Fiber Channel";
case PCI_SERIAL_SMBUS: return "SMBus";
case PCI_WIRELESS_IRDA: return "iRDA Compatible Controller";
case PCI_WIRLESSS_IR: return "Consumer IR Controller";
case PCI_WIRLESSS_RF: return "RF Controller";
case PCI_WIRLESSS_BLUETOOTH: return "Bluetooth";
case PCI_WIRLESSS_BROADBAND: return "Broadband";
case PCI_WIRLESSS_ETHERNET_A: return "802.1a Controller";
case PCI_WIRLESSS_ETHERNET_B: return "802.1b Controller";
case PCI_WIRELESS_OTHER: return "Wireless Controller";
case PCI_INTELLIGENT_I2O: return "I2O Controller";
case PCI_SATELLITE_TV: return "Satellite TV Controller";
case PCI_SATELLITE_AUDIO: return "Satellite Audio Controller";
case PCI_SATELLITE_VOICE: return "Satellite Voice Controller";
case PCI_SATELLITE_DATA: return "Satellite Data Controller";
case PCI_CRYPT_NETWORK: return "Network and Computing Encryption Device";
case PCI_CRYPT_ENTERTAINMENT: return "Entertainment Encryption Device";
case PCI_CRYPT_OTHER: return "Encryption Device";
case PCI_SP_DPIO: return "DPIO Modules";
case PCI_SP_OTHER: return "Signal Processing Controller";
}
return "Unknown PCI Class";
}

169
kernel/pci/reg.h
View File

@ -1,169 +0,0 @@
#ifndef PCI_REG_H_
#define PCI_REG_H_
#include <stdint.h>
#include <stddef.h>
// PCI Vendors
#define PCI_VENDOR_INTEL 0x8086
// PCI Classes
#define PCI_CLASS_LEGACY 0x00
#define PCI_CLASS_STORAGE 0x01
#define PCI_CLASS_NETWORK 0x02
#define PCI_CLASS_DISPLAY 0x03
#define PCI_CLASS_MULTIMEDIA 0x04
#define PCI_CLASS_MEMORY 0x05
#define PCI_CLASS_BRIDGE_DEVICE 0x06
#define PCI_CLASS_COMMUNICATION 0x07
#define PCI_CLASS_PERIHPERALS 0x08
#define PCI_CLASS_INPUT_DEVICES 0x09
#define PCI_CLASS_DOCKING_STATION 0x0a
#define PCI_CLASS_PROCESSOR 0x0b
#define PCI_CLASS_SERIAL_BUS 0x0c
#define PCI_CLASS_WIRELESS 0x0d
#define PCI_CLASS_INTELLIGENT_IO 0x0e
#define PCI_CLASS_SATELLITE 0x0f
#define PCI_CLASS_CRYPT 0x10
#define PCI_CLASS_SIGNAL_PROCESSING 0x11
#define PCI_CLASS_UNDEFINED 0xff
// Undefined Class
#define PCI_UNCLASSIFIED 0x0000
#define PCI_VGA_COMPATIBLE 0x0001
// Mass Storage Controller
#define PCI_STORAGE_SCSI 0x0100
#define PCI_STORAGE_IDE 0x0101
#define PCI_STORAGE_FLOPPY 0x0102
#define PCI_STORAGE_IPI 0x0103
#define PCI_STORAGE_RAID 0x0104
#define PCI_STORAGE_ATA 0x0105
#define PCI_STORAGE_SATA 0x0106
#define PCI_STORAGE_OTHER 0x0180
// Network Controller
#define PCI_NETWORK_ETHERNET 0x0200
#define PCI_NETWORK_TOKEN_RING 0x0201
#define PCI_NETWORK_FDDI 0x0202
#define PCI_NETWORK_ATM 0x0203
#define PCI_NETWORK_ISDN 0x0204
#define PCI_NETWORK_WORLDFIP 0x0205
#define PCI_NETWORK_PICGMG 0x0206
#define PCI_NETWORK_OTHER 0x0280
// Display Controller
#define PCI_DISPLAY_VGA 0x0300
#define PCI_DISPLAY_XGA 0x0301
#define PCI_DISPLAY_3D 0x0302
#define PCI_DISPLAY_OTHER 0x0380
// Multimedia Controller
#define PCI_MULTIMEDIA_VIDEO 0x0400
#define PCI_MULTIMEDIA_AUDIO 0x0401
#define PCI_MULTIMEDIA_PHONE 0x0402
#define PCI_MULTIMEDIA_AUDIO_DEVICE 0x0403
#define PCI_MULTIMEDIA_OTHER 0x0480
// Memory Controller
#define PCI_MEMORY_RAM 0x0500
#define PCI_MEMORY_FLASH 0x0501
#define PCI_MEMORY_OTHER 0x0580
// Bridge Device
#define PCI_BRIDGE_HOST 0x0600
#define PCI_BRIDGE_ISA 0x0601
#define PCI_BRIDGE_EISA 0x0602
#define PCI_BRIDGE_MCA 0x0603
#define PCI_BRIDGE_PCI 0x0604
#define PCI_BRIDGE_PCMCIA 0x0605
#define PCI_BRIDGE_NUBUS 0x0606
#define PCI_BRIDGE_CARDBUS 0x0607
#define PCI_BRIDGE_RACEWAY 0x0608
#define PCI_BRIDGE_OTHER 0x0680
// Simple Communication Controller
#define PCI_COMM_SERIAL 0x0700
#define PCI_COMM_PARALLEL 0x0701
#define PCI_COMM_MULTIPORT 0x0702
#define PCI_COMM_MODEM 0x0703
#define PCI_COMM_GPIB 0x0704
#define PCI_COMM_SMARTCARD 0x0705
#define PCI_COMM_OTHER 0x0780
// Base System Peripherals
#define PCI_SYSTEM_PIC 0x0800
#define PCI_SYSTEM_DMA 0x0801
#define PCI_SYSTEM_TIMER 0x0802
#define PCI_SYSTEM_RTC 0x0803
#define PCI_SYSTEM_PCI_HOTPLUG 0x0804
#define PCI_SYSTEM_SD 0x0805
#define PCI_SYSTEM_OTHER 0x0880
// Input Devices
#define PCI_INPUT_KEYBOARD 0x0900
#define PCI_INPUT_PEN 0x0901
#define PCI_INPUT_MOUSE 0x0902
#define PCI_INPUT_SCANNER 0x0903
#define PCI_INPUT_GAMEPORT 0x0904
#define PCI_INPUT_OTHER 0x0980
// Docking Stations
#define PCI_DOCKING_GENERIC 0x0a00
#define PCI_DOCKING_OTHER 0x0a80
// Processors
#define PCI_PROCESSOR_386 0x0b00
#define PCI_PROCESSOR_486 0x0b01
#define PCI_PROCESSOR_PENTIUM 0x0b02
#define PCI_PROCESSOR_ALPHA 0x0b10
#define PCI_PROCESSOR_POWERPC 0x0b20
#define PCI_PROCESSOR_MIPS 0x0b30
#define PCI_PROCESSOR_CO 0x0b40
// Serial Bus Controllers
#define PCI_SERIAL_FIREWIRE 0x0c00
#define PCI_SERIAL_ACCESS 0x0c01
#define PCI_SERIAL_SSA 0x0c02
#define PCI_SERIAL_USB 0x0c03
#define PCI_SERIAL_FIBER 0x0c04
#define PCI_SERIAL_SMBUS 0x0c05
#define PCI_SERIAL_USB_UHCI 0x00
#define PCI_SERIAL_USB_OHCI 0x10
#define PCI_SERIAL_USB_EHCI 0x20
#define PCI_SERIAL_USB_XHCI 0x30
#define PCI_SERIAL_USB_OTHER 0x80
// Wireless Controllers
#define PCI_WIRELESS_IRDA 0x0d00
#define PCI_WIRLESSS_IR 0x0d01
#define PCI_WIRLESSS_RF 0x0d10
#define PCI_WIRLESSS_BLUETOOTH 0x0d11
#define PCI_WIRLESSS_BROADBAND 0x0d12
#define PCI_WIRLESSS_ETHERNET_A 0x0d20
#define PCI_WIRLESSS_ETHERNET_B 0x0d21
#define PCI_WIRELESS_OTHER 0x0d80
// Intelligent I/O Controllers
#define PCI_INTELLIGENT_I2O 0x0e00
// Satellite Communication Controllers
#define PCI_SATELLITE_TV 0x0f00
#define PCI_SATELLITE_AUDIO 0x0f01
#define PCI_SATELLITE_VOICE 0x0f03
#define PCI_SATELLITE_DATA 0x0f04
// Encryption/Decryption Controllers
#define PCI_CRYPT_NETWORK 0x1000
#define PCI_CRYPT_ENTERTAINMENT 0x1001
#define PCI_CRYPT_OTHER 0x1080
// Data Acquisition and Signal Processing Controllers
#define PCI_SP_DPIO 0x1100
#define PCI_SP_OTHER 0x1180
const char *pci_devname(uint32_t vendorid, uint32_t deviceid);
const char *pci_classname(uint32_t classcode, uint32_t subclass, uint32_t progintf);
#endif // PCI_REG_H_

2
run/qemu-x86_64-hdd.sh
View File

@ -7,5 +7,5 @@ qemu-system-x86_64 \
-m 4G \
-boot d \
-serial stdio \
-drive file=disk.hdd,format=raw,if=ide \
-hda disk.hdd
$@