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241 lines
7.0 KiB
C
241 lines
7.0 KiB
C
#include <amd64/apic.h>
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#include <amd64/gdt.h>
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#include <amd64/intr.h>
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#include <amd64/intr_defs.h>
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#include <amd64/io.h>
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#include <aux/compiler.h>
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#include <irq/irq.h>
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#include <libk/std.h>
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#include <libk/string.h>
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#include <sys/debug.h>
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#include <sys/irq.h>
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#include <sys/smp.h>
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#include <sys/spin.h>
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/* 8259 PIC defs. */
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#define PIC1 0x20
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#define PIC2 0xA0
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#define PIC1_CMD PIC1
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#define PIC1_DATA (PIC1 + 1)
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#define PIC2_CMD PIC2
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#define PIC2_DATA (PIC2 + 1)
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#define PIC_EOI 0x20
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#define ICW1_ICW4 0x01
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#define ICW1_SINGLE 0x02
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#define ICW1_INTVL4 0x04
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#define ICW1_LEVEL 0x08
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#define ICW1_INIT 0x10
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#define ICW4_8086 0x01
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#define ICW4_AUTO 0x02
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#define ICW4_BUFSLAVE 0x08
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#define ICW4_BUFMASER 0x0C
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#define ICW4_SFNM 0x10
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#define CASCADE_IRQ 2
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/* IDT defs. */
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#define IDT_ENTRIES_MAX 256
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/// 64-bit <IDT entry structure: https://wiki.osdev.org/Interrupt_Descriptor_Table
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struct idt_entry {
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uint16_t intrlow;
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uint16_t kernel_cs;
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uint8_t ist;
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uint8_t attrs;
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uint16_t intrmid;
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uint32_t intrhigh;
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uint32_t resv;
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} PACKED;
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struct idt {
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uint16_t limit;
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uint64_t base;
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} PACKED;
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/** @cond DOXYGEN_IGNORE */
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ALIGNED (16) static volatile struct idt_entry idt_entries[IDT_ENTRIES_MAX];
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/** @endcond */
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static volatile struct idt idt;
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/// Remaps and disables old 8259 PIC, since we'll be using APIC.
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static void amd64_init_pic (void) {
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/** @cond DOXYGEN_IGNORE */
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#define IO_OP(fn, ...) \
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fn (__VA_ARGS__); \
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amd64_io_wait ()
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/** @endcond */
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IO_OP (amd64_io_outb, PIC1_CMD, (ICW1_INIT | ICW1_ICW4));
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IO_OP (amd64_io_outb, PIC2_CMD, (ICW1_INIT | ICW1_ICW4));
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IO_OP (amd64_io_outb, PIC1_DATA, 0x20);
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IO_OP (amd64_io_outb, PIC2_DATA, 0x28);
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IO_OP (amd64_io_outb, PIC1_DATA, (1 << CASCADE_IRQ));
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IO_OP (amd64_io_outb, PIC2_DATA, 2);
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IO_OP (amd64_io_outb, PIC1_DATA, ICW4_8086);
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IO_OP (amd64_io_outb, PIC2_DATA, ICW4_8086);
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/* Disable */
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IO_OP (amd64_io_outb, PIC1_DATA, 0xFF);
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IO_OP (amd64_io_outb, PIC2_DATA, 0xFF);
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#undef IO_OP
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}
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/// Set IDT entry
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static void amd64_idt_set (volatile struct idt_entry* ent, uint64_t handler, uint8_t flags,
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uint8_t ist) {
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ent->intrlow = (handler & 0xFFFF);
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ent->kernel_cs = GDT_KCODE;
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ent->ist = ist;
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ent->attrs = flags;
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ent->intrmid = ((handler >> 16) & 0xFFFF);
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ent->intrhigh = ((handler >> 32) & 0xFFFFFFFF);
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ent->resv = 0;
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}
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/// Load the IDT
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void amd64_load_idt (void) { __asm__ volatile ("lidt %0" ::"m"(idt)); }
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/// Initialize IDT entries
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static void amd64_idt_init (void) {
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memset ((void*)idt_entries, 0, sizeof (idt_entries));
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/** @cond DOXYGEN_IGNORE */
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#define IDT_ENTRY(n, ist) \
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extern void amd64_intr##n (void); \
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amd64_idt_set (&idt_entries[(n)], (uint64_t)&amd64_intr##n, 0x8E, (ist))
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/** @endcond */
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/* clang-format off */
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IDT_ENTRY (0, 0); IDT_ENTRY (1, 0); IDT_ENTRY (2, 0); IDT_ENTRY (3, 0);
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IDT_ENTRY (4, 0); IDT_ENTRY (5, 0); IDT_ENTRY (6, 0); IDT_ENTRY (7, 0);
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IDT_ENTRY (8, 0); IDT_ENTRY (9, 0); IDT_ENTRY (10, 0); IDT_ENTRY (11, 0);
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IDT_ENTRY (12, 0); IDT_ENTRY (13, 0); IDT_ENTRY (14, 0); IDT_ENTRY (15, 0);
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IDT_ENTRY (16, 0); IDT_ENTRY (17, 0); IDT_ENTRY (18, 0); IDT_ENTRY (19, 0);
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IDT_ENTRY (20, 0); IDT_ENTRY (21, 0); IDT_ENTRY (22, 0); IDT_ENTRY (23, 0);
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IDT_ENTRY (24, 0); IDT_ENTRY (25, 0); IDT_ENTRY (26, 0); IDT_ENTRY (27, 0);
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IDT_ENTRY (28, 0); IDT_ENTRY (29, 0); IDT_ENTRY (30, 0); IDT_ENTRY (31, 0);
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IDT_ENTRY (32, 1); IDT_ENTRY (33, 1); IDT_ENTRY (34, 1); IDT_ENTRY (35, 1);
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IDT_ENTRY (36, 1); IDT_ENTRY (37, 1); IDT_ENTRY (38, 1); IDT_ENTRY (39, 1);
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IDT_ENTRY (40, 1); IDT_ENTRY (41, 1); IDT_ENTRY (42, 1); IDT_ENTRY (43, 1);
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IDT_ENTRY (44, 1); IDT_ENTRY (45, 1); IDT_ENTRY (46, 1); IDT_ENTRY (47, 1);
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IDT_ENTRY (SCHED_PREEMPT_TIMER, 1);
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IDT_ENTRY (TLB_SHOOTDOWN, 1);
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/* clang-format on */
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#undef IDT_ENTRY
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idt.limit = sizeof (idt_entries) - 1;
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idt.base = (uint64_t)idt_entries;
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amd64_load_idt ();
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}
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/**
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* @brief Handle CPU exception and dump registers. If incoming CS has CPL3, kill the
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* process.
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*
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* @param regs
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* saved registers
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*/
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static void amd64_intr_exception (struct saved_regs* regs) {
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DEBUG ("cpu exception %lu (%lu)\n", regs->trap, regs->error);
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uint64_t cr2;
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__asm__ volatile ("movq %%cr2, %0" : "=r"(cr2));
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uint64_t cr3;
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__asm__ volatile ("movq %%cr3, %0" : "=r"(cr3));
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debugprintf ("r15=%016lx r14=%016lx r13=%016lx\n"
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"r12=%016lx r11=%016lx r10=%016lx\n"
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"r9 =%016lx r8 =%016lx rbp=%016lx\n"
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"rdi=%016lx rsi=%016lx rdx=%016lx\n"
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"rcx=%016lx rax=%016lx trp=%016lx\n"
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"err=%016lx rip=%016lx cs =%016lx\n"
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"rfl=%016lx rsp=%016lx ss =%016lx\n"
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"cr2=%016lx cr3=%016lx rbx=%016lx\n",
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regs->r15, regs->r14, regs->r13, regs->r12, regs->r11, regs->r10, regs->r9, regs->r8,
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regs->rbp, regs->rdi, regs->rsi, regs->rdx, regs->rcx, regs->rax, regs->trap,
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regs->error, regs->rip, regs->cs, regs->rflags, regs->rsp, regs->ss, cr2, cr3,
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regs->rbx);
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if (regs->cs == (GDT_UCODE | 0x03)) {
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proc_kill (thiscpu->proc_current);
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} else {
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spin ();
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}
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}
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/// Handle incoming interrupt, dispatch IRQ handlers.
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void amd64_intr_handler (void* stack_ptr) {
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struct saved_regs* regs = stack_ptr;
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if (regs->trap <= 31) {
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amd64_intr_exception (regs);
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} else {
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amd64_lapic_eoi ();
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struct irq* irq = irq_find (regs->trap);
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if (irq != NULL) {
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if ((irq->flags & IRQ_INTERRUPT_SAFE))
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__asm__ volatile ("sti");
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irq->func (irq->arg, stack_ptr);
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if ((irq->flags & IRQ_INTERRUPT_SAFE))
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__asm__ volatile ("cli");
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}
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}
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}
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/// Initialize interrupts
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void amd64_intr_init (void) {
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amd64_init_pic ();
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amd64_idt_init ();
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}
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/* Aux. */
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/// Save RFLAGS of the current CPU
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static uint64_t amd64_irq_save_flags (void) {
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uint64_t rflags;
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__asm__ volatile ("pushfq; cli; popq %0" : "=r"(rflags)::"memory", "cc");
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return rflags;
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}
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/// Restore interrupts (IF bit) from RFLAGS
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static void amd64_irq_restore_flags (uint64_t rflags) {
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if (rflags & (1ULL << 9))
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__asm__ volatile ("sti");
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}
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/// Save current interrupt state
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void irq_save (void) {
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int prev = atomic_fetch_add_explicit (&thiscpu->irq_ctx.nesting, 1, memory_order_acq_rel);
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if (prev == 0)
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thiscpu->irq_ctx.rflags = amd64_irq_save_flags ();
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}
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/// Restore interrupt state
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void irq_restore (void) {
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int prev = atomic_fetch_sub_explicit (&thiscpu->irq_ctx.nesting, 1, memory_order_acq_rel);
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if (prev == 1)
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amd64_irq_restore_flags (thiscpu->irq_ctx.rflags);
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}
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/// Map custom IRQ mappings to legacy IRQs
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uint8_t amd64_resolve_irq (uint8_t irq) {
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static const uint8_t mappings[] = {
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[SCHED_PREEMPT_TIMER] = 0,
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[TLB_SHOOTDOWN] = 1,
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};
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return mappings[irq];
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}
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