513 lines
12 KiB
C
513 lines
12 KiB
C
#ifndef SYS__CPU_H__
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#define SYS__CPU_H__
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#include <stdint.h>
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#include <stddef.h>
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#include <stdbool.h>
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#if defined(__x86_64__) || defined(__i386__)
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static inline bool cpuid(uint32_t leaf, uint32_t subleaf,
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uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx) {
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uint32_t cpuid_max;
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asm volatile ("cpuid"
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: "=a" (cpuid_max)
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: "a" (leaf & 0x80000000)
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: "ebx", "ecx", "edx");
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if (leaf > cpuid_max)
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return false;
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asm volatile ("cpuid"
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: "=a" (*eax), "=b" (*ebx), "=c" (*ecx), "=d" (*edx)
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: "a" (leaf), "c" (subleaf));
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return true;
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}
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static inline void outb(uint16_t port, uint8_t value) {
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asm volatile ("outb %%al, %1" : : "a" (value), "Nd" (port) : "memory");
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}
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static inline void outw(uint16_t port, uint16_t value) {
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asm volatile ("outw %%ax, %1" : : "a" (value), "Nd" (port) : "memory");
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}
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static inline void outd(uint16_t port, uint32_t value) {
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asm volatile ("outl %%eax, %1" : : "a" (value), "Nd" (port) : "memory");
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}
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static inline uint8_t inb(uint16_t port) {
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uint8_t value;
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asm volatile ("inb %1, %%al" : "=a" (value) : "Nd" (port) : "memory");
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return value;
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}
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static inline uint16_t inw(uint16_t port) {
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uint16_t value;
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asm volatile ("inw %1, %%ax" : "=a" (value) : "Nd" (port) : "memory");
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return value;
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}
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static inline uint32_t ind(uint16_t port) {
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uint32_t value;
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asm volatile ("inl %1, %%eax" : "=a" (value) : "Nd" (port) : "memory");
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return value;
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}
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static inline void mmoutb(uintptr_t addr, uint8_t value) {
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asm volatile (
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"movb %1, (%0)"
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:
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: "r" (addr), "ir" (value)
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: "memory"
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);
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}
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static inline void mmoutw(uintptr_t addr, uint16_t value) {
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asm volatile (
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"movw %1, (%0)"
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:
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: "r" (addr), "ir" (value)
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: "memory"
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);
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}
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static inline void mmoutd(uintptr_t addr, uint32_t value) {
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asm volatile (
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"movl %1, (%0)"
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:
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: "r" (addr), "ir" (value)
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: "memory"
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);
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}
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#if defined (__x86_64__)
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static inline void mmoutq(uintptr_t addr, uint64_t value) {
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asm volatile (
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"movq %1, (%0)"
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:
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: "r" (addr), "r" (value)
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: "memory"
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);
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}
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#endif
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static inline uint8_t mminb(uintptr_t addr) {
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uint8_t ret;
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asm volatile (
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"movb (%1), %0"
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: "=r" (ret)
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: "r" (addr)
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: "memory"
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);
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return ret;
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}
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static inline uint16_t mminw(uintptr_t addr) {
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uint16_t ret;
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asm volatile (
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"movw (%1), %0"
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: "=r" (ret)
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: "r" (addr)
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: "memory"
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);
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return ret;
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}
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static inline uint32_t mmind(uintptr_t addr) {
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uint32_t ret;
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asm volatile (
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"movl (%1), %0"
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: "=r" (ret)
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: "r" (addr)
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: "memory"
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);
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return ret;
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}
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#if defined (__x86_64__)
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static inline uint64_t mminq(uintptr_t addr) {
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uint64_t ret;
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asm volatile (
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"movq (%1), %0"
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: "=r" (ret)
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: "r" (addr)
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: "memory"
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);
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return ret;
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}
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#endif
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static inline uint64_t rdmsr(uint32_t msr) {
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uint32_t edx, eax;
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asm volatile ("rdmsr"
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: "=a" (eax), "=d" (edx)
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: "c" (msr)
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: "memory");
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return ((uint64_t)edx << 32) | eax;
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}
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static inline void wrmsr(uint32_t msr, uint64_t value) {
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uint32_t edx = value >> 32;
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uint32_t eax = (uint32_t)value;
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asm volatile ("wrmsr"
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:
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: "a" (eax), "d" (edx), "c" (msr)
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: "memory");
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}
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static inline uint64_t rdtsc(void) {
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uint32_t edx, eax;
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asm volatile ("rdtsc" : "=a" (eax), "=d" (edx) :: "memory");
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return ((uint64_t)edx << 32) | eax;
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}
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static inline uint64_t tsc_freq_arch(void) {
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uint32_t eax, ebx, ecx, edx;
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if (!cpuid(0x15, 0, &eax, &ebx, &ecx, &edx))
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return 0;
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if (eax == 0 || ebx == 0 || ecx == 0)
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return 0;
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return (uint64_t)ecx * ebx / eax;
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}
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#define rdrand(type) ({ \
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type rdrand__ret = 0; \
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for (int rdrand__i = 0; rdrand__i < 10; rdrand__i++) { \
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bool rdrand__ok; \
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asm volatile ( \
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"rdrand %0; setc %1" \
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: "=r" (rdrand__ret), "=qm" (rdrand__ok) \
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); \
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if (rdrand__ok) break; \
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} \
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rdrand__ret; \
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})
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#define rdseed(type) ({ \
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type rdseed__ret = 0; \
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for (int rdseed__i = 0; rdseed__i < 10; rdseed__i++) { \
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bool rdseed__ok; \
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asm volatile ( \
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"rdseed %0; setc %1" \
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: "=r" (rdseed__ret), "=qm" (rdseed__ok) \
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); \
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if (rdseed__ok) break; \
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} \
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rdseed__ret; \
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})
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#define write_cr(reg, val) do { \
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asm volatile ("mov %0, %%cr" reg :: "r" (val) : "memory"); \
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} while (0)
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#define read_cr(reg) ({ \
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size_t read_cr__cr; \
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asm volatile ("mov %%cr" reg ", %0" : "=r" (read_cr__cr) :: "memory"); \
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read_cr__cr; \
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})
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#define locked_read(var) ({ \
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typeof(*var) locked_read__ret = 0; \
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asm volatile ( \
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"lock xadd %0, %1" \
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: "+r" (locked_read__ret), "+m" (*(var)) \
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:: "memory" \
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); \
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locked_read__ret; \
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})
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#define locked_write(var, val) do { \
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__auto_type locked_write__ret = val; \
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asm volatile ( \
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"lock xchg %0, %1" \
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: "+r" ((locked_write__ret)) \
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: "m" (*(var)) \
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: "memory" \
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); \
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} while (0)
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#elif defined (__aarch64__)
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static inline uint64_t rdtsc(void) {
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uint64_t v;
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asm volatile ("mrs %0, cntpct_el0" : "=r" (v));
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return v;
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}
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static inline uint64_t tsc_freq_arch(void) {
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uint64_t v;
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asm volatile ("mrs %0, cntfrq_el0" : "=r" (v));
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return v;
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}
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#define locked_read(var) ({ \
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typeof(*var) locked_read__ret = 0; \
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asm volatile ( \
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"ldar %0, %1" \
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: "=r" (locked_read__ret) \
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: "Q" (*(var)) \
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: "memory" \
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); \
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locked_read__ret; \
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})
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static inline size_t icache_line_size(void) {
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uint64_t ctr;
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asm volatile ("mrs %0, ctr_el0" : "=r"(ctr));
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return 4 << (ctr & 0b1111);
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}
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static inline size_t dcache_line_size(void) {
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uint64_t ctr;
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asm volatile ("mrs %0, ctr_el0" : "=r"(ctr));
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return 4 << ((ctr >> 16) & 0b1111);
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}
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static inline bool is_icache_pipt(void) {
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uint64_t ctr;
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asm volatile ("mrs %0, ctr_el0" : "=r"(ctr));
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return ((ctr >> 14) & 0b11) == 0b11;
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}
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// Clean D-Cache to Point of Coherency
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static inline void clean_dcache_poc(uintptr_t start, uintptr_t end) {
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size_t dsz = dcache_line_size();
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uintptr_t addr = start & ~(dsz - 1);
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while (addr < end) {
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asm volatile ("dc cvac, %0" :: "r"(addr) : "memory");
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addr += dsz;
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}
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asm volatile ("dsb sy\n\tisb");
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}
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// Invalidate I-Cache to Point of Unification
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static inline void inval_icache_pou(uintptr_t start, uintptr_t end) {
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if (!is_icache_pipt()) {
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asm volatile ("ic ialluis" ::: "memory");
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asm volatile ("dsb sy\n\tisb");
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return;
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}
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size_t isz = icache_line_size();
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uintptr_t addr = start & ~(isz - 1);
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while (addr < end) {
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asm volatile ("ic ivau, %0" :: "r"(addr) : "memory");
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addr += isz;
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}
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asm volatile ("dsb sy\n\tisb");
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}
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static inline int current_el(void) {
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uint64_t v;
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asm volatile ("mrs %0, currentel" : "=r"(v));
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v = (v >> 2) & 0b11;
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return v;
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}
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#elif defined (__riscv)
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static inline uint64_t rdtsc(void) {
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uint64_t v;
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asm volatile ("rdtime %0" : "=r"(v));
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return v;
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}
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uint64_t riscv_time_base_frequency(void);
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static inline uint64_t tsc_freq_arch(void) {
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return riscv_time_base_frequency();
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}
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#define csr_read(csr) ({\
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size_t v;\
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asm volatile ("csrr %0, " csr : "=r"(v));\
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v;\
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})
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#define csr_write(csr, v) ({\
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size_t old;\
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asm volatile ("csrrw %0, " csr ", %1" : "=r"(old) : "r"(v));\
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old;\
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})
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#define make_satp(mode, ppn) (((size_t)(mode) << 60) | ((size_t)(ppn) >> 12))
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#define locked_read(var) ({ \
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typeof(*var) locked_read__ret; \
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asm volatile ( \
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"ld %0, (%1); fence r, rw" \
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: "=r"(locked_read__ret) \
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: "r"(var) \
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: "memory" \
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); \
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locked_read__ret; \
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})
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extern size_t bsp_hartid;
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struct riscv_hart {
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struct riscv_hart *next;
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const char *isa_string;
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size_t hartid;
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uint32_t acpi_uid;
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uint8_t mmu_type;
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uint8_t flags;
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};
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#define RISCV_HART_COPROC ((uint8_t)1 << 0) // is a coprocessor
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#define RISCV_HART_HAS_MMU ((uint8_t)1 << 1) // `mmu_type` field is valid
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extern struct riscv_hart *hart_list;
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extern struct riscv_hart *bsp_hart;
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bool riscv_check_isa_extension_for(size_t hartid, const char *ext, size_t *maj, size_t *min);
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static inline bool riscv_check_isa_extension(const char *ext, size_t *maj, size_t *min) {
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return riscv_check_isa_extension_for(bsp_hartid, ext, maj, min);
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}
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void init_riscv(const char *config);
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#elif defined (__loongarch64)
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#define csr_read64(reg) ({ \
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uint64_t csr_read64__ret; \
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asm volatile ( \
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"csrrd %0, %1" \
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: "=r"(csr_read64__ret) \
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: "i"(reg) \
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); \
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csr_read64__ret; \
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})
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#define csr_write64(val, reg) do { \
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__auto_type csr_write64__val = (val); \
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asm volatile ( \
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"csrwr %0, %1" \
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: \
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: "r"(csr_write64__val), "i"(reg) \
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: "memory" \
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); \
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} while (0)
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#define csr_read32(reg) ((uint32_t)csr_read64(reg))
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#define csr_write32(val, reg) do { \
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csr_write64((uint64_t)(val), reg); \
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} while (0)
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#define csr_xchg64(val, mask, reg) ({ \
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uint64_t csr_xchg64__ret = (uint64_t)(val); \
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uint64_t csr_xchg64__mask = (uint64_t)(mask); \
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asm volatile ( \
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"csrxchg %0, %1, %2" \
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: "+r"(csr_xchg64__ret) \
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: "r"(csr_xchg64__mask), "i"(reg) \
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: "memory" \
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); \
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csr_xchg64__ret; \
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})
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#define locked_read(var) ({ \
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typeof(*var) locked_read__ret; \
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asm volatile ( \
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"ld.d %0, %1\n\t" \
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"dbar 0" \
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: "=r"(locked_read__ret) \
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: "m"(*(var)) \
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: "memory" \
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); \
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locked_read__ret; \
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})
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static inline uint32_t iocsr_read32(uint64_t reg) {
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uint32_t val;
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asm volatile (
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"iocsrrd.w %0, %1"
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: "=r"(val)
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: "r"(reg)
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);
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return val;
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}
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static inline void iocsr_write32(uint32_t val, uint64_t reg) {
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asm volatile (
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"iocsrwr.w %0, %1"
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:
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: "r"(val), "r"(reg)
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);
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}
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static inline uint64_t iocsr_read64(uint64_t reg) {
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uint64_t val;
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asm volatile (
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"iocsrrd.d %0, %1"
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: "=r"(val)
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: "r"(reg)
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);
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return val;
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}
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static inline void iocsr_write64(uint64_t val, uint64_t reg) {
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asm volatile (
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"iocsrwr.d %0, %1"
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:
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: "r"(val), "r"(reg)
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);
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}
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static inline uint64_t rdtsc(void) {
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uint64_t v;
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asm volatile ("rdtime.d %0, $zero" : "=r" (v));
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return v;
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}
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static inline uint32_t loongarch_cpucfg(uint32_t reg) {
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uint32_t v;
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asm volatile ("cpucfg %0, %1" : "=r" (v) : "r" (reg));
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return v;
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}
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static inline uint64_t tsc_freq_arch(void) {
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uint32_t cc_freq = loongarch_cpucfg(4);
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uint32_t cc_cfg = loongarch_cpucfg(5);
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uint32_t cc_mul = cc_cfg & 0xFFFF;
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uint32_t cc_div = (cc_cfg >> 16) & 0xFFFF;
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if (cc_freq == 0 || cc_mul == 0 || cc_div == 0) {
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return 0;
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}
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return (uint64_t)cc_freq * cc_mul / cc_div;
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}
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#else
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#error Unknown architecture
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#endif
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extern uint64_t tsc_freq;
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void calibrate_tsc(void);
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static inline uint64_t rdtsc_usec(void) {
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uint64_t exec_ticks = rdtsc();
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if (tsc_freq == 0) {
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return 0;
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}
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return exec_ticks / tsc_freq * 1000000
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+ exec_ticks % tsc_freq * 1000000 / tsc_freq;
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}
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static inline void stall(uint64_t us) {
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uint64_t ticks = (tsc_freq * us + 999999) / 1000000;
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uint64_t next_stop = rdtsc() + ticks;
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while (rdtsc() < next_stop);
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}
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#endif
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