Commit Graph

33 Commits

Author SHA1 Message Date
Mintsuki
8e842edecf sys/cpu: Add PIT-based TSC calibration for BIOS 2026-04-06 19:04:22 +02:00
Mintsuki
dd2354bae9 sys/cpu: Add retry limit to rdrand/rdseed macros 2026-04-02 22:21:54 +02:00
Mintsuki
f7c265f806 sys/cpu: Fix locked_read memory operand constraint to input+output 2026-04-02 01:44:58 +02:00
Mintsuki
b58da8372a Merge pull request 'loongarch64: Add smp support' (#50) from lihanrui/Limine:trunk into trunk
Reviewed-on: https://codeberg.org/Limine/Limine/pulls/50
2026-03-18 11:08:35 +01:00
Mintsuki
ae7399eb8e sys/cpu: Use Q constraint for aarch64 locked_read to avoid ldar offset 2026-03-16 00:12:19 +01:00
Mintsuki
706bbac234 sys/cpu: Round up stall() tick count for sub-MHz timer frequencies 2026-02-25 04:09:06 +01:00
Mintsuki
aad4f66fec sys/cpu: Fix rdtsc_usec() intermediate overflow 2026-02-25 04:09:06 +01:00
Mintsuki
c5c2e7909e sys/cpu: Add memory clobber to rdtsc inline assembly 2026-02-25 04:09:05 +01:00
Mintsuki
66d6d8402d sys/cpu: Fix integer truncation in stall() 2026-02-22 18:29:01 +01:00
Mintsuki
9d3e231834 sys/cpu: Replace cycle-based delay() with calibrated stall() 2026-02-17 08:07:11 +01:00
lihanrui2913
57ae8f017a loongarch64: Add smp support 2026-02-15 10:29:09 +08:00
Mintsuki
e700741d9e sys/cpu: Use rdtime.d and CPUCFG for LoongArch64 performance timing 2026-02-09 13:02:39 +01:00
Mintsuki
f6de46a7fc sys/cpu: Use rdtime and time_base_frequency for RISC-V performance timing 2026-02-09 13:02:39 +01:00
Mintsuki
3a609b166a mm/vmm: Use firmware-reported MMU type instead of satp probe on RISC-V 2026-02-09 13:02:39 +01:00
Mintsuki
a5eba5a073 sys/cpu: Fix 32-bit multiplication overflow in tsc_freq_arch 2026-02-09 13:02:39 +01:00
Mintsuki
190283949c sys/cpu: Fix AArch64 cache line size calculation to use 4 << field 2026-02-09 13:02:38 +01:00
Kacper Słomiński
02f1a8f539 sys/cpu: Flush entire I-Cache if it's not PIPT on aarch64
AArch64 permits the I-Cache be either PIPT or VIPT. In the latter
case, flush by VA might leave aliases at other VAs in the cache. I
don't expect there to be any since we're using an identity mapping at
this point, but this doesn't hurt.
2025-11-29 17:21:49 +01:00
sanana
c411051252 lib/bli: Implement LoaderTimeInitUSec and LoaderTimeExecUSec
These are variables used by `systemd-analyze` and is useful for boot performance
metrics.
2025-07-03 11:02:54 +03:00
sanana
957661c7ea sys/cpu: Implement TSC frequency calibration
`tsc_freq_arch` is the architecture-specific function to get the frequency of
rdtsc. If that fails (e.g. on an x86_64 machine without CPUID leaf 0x15) then
the TSC is calibrated with EFI Boot Services' `Stall`.
2025-06-29 15:11:14 +03:00
Kacper Słomiński
945c43de0d lib: Move DTB_PATH handling logic into common code 2024-12-24 17:10:47 +01:00
mintsuki
0c2f0ddebe build: Remove custom __riscv64 define in favour of built-in __riscv define
We do not support non-64-bit RISC-V anyways
2024-08-11 20:25:01 +02:00
mintsuki
6eecac7049 riscv64: Use rdcycle instead of rdtime for rdtsc(); add delay to SMP startup like 530e28e846 2024-08-09 14:45:21 +02:00
Kacper Słomiński
530e28e846 smp: Fix BSP timing out while waiting for APs on AArch64
When running with KVM, the BSP seems to time out while waiting for APs
to come up, which leads to the OS only being told about 1 AP, and
all the APs using the same info struct and stack pointer.
2024-08-09 08:21:15 +02:00
Keegan Saunders
d9a2fb95a9 Add LoongArch support 2024-07-31 23:05:27 -04:00
mintsuki
4e4105782e misc: No more non-static inline functions in headers 2024-04-10 20:16:37 +02:00
cospplredman
ba5c0004e6 fixed header guard names
made them more standard compliant
2024-03-20 03:06:55 +01:00
xvanc
f33732a2e5 riscv: implement feature dectection 2023-09-16 11:21:17 -05:00
Kacper Słomiński
50dab6c2f1 smp: aarch64: Don't needlessly invalidate the data cache
Also get rid of the function to do clean + invalidate as not to be
tempted by it.
2023-08-18 13:38:14 -05:00
Kacper Słomiński
ba5d63b82a elf: aarch64: Don't needlessly invalidate the data cache
Cleaning the data cache to PoC without invalidating it is enough when
invalidating the instruction cache to PoU.
2023-08-18 13:37:55 -05:00
xvanc
9274ee656e Initial riscv64 port (#274)
* initial riscv64 port

* enable Paging Mode feature for all architectures

* riscv: add missing protocol docs

* riscv: fix tests

* docs: clarify `LIMINE_PAGING_MODE_DEFAULT` macro

* build: fix whitespace in common/GNUmakefile

* riscv: default to Sv48 paging when supported

* vmm: make `VMM_MAX_LEVEL` 1-indexed

* limine: do not call `reported_addr()` before finaling paging mode

smp/riscv: do not overwrite the argument passed to APs

* limine/riscv: update default paging mode in limine.h

* test/riscv: pad OVMF.fd when downloading it
2023-06-04 01:36:06 +02:00
mintsuki
65671d73c7 misc: Update several macros 2022-08-26 23:30:00 +02:00
Kacper Słomiński
e1f6ac8860 Initial AArch64 port (#205)
* Initial aarch64 port

* Enable chainload on aarch64

No changes necessary since it's all UEFI anyway.

* Add specification for Limine protocol for aarch64

* PROTOCOL: Specify state of information in DT /chosen node

* common: Add spinup code for aarch64

* common: Port elf and term to aarch64

* common: Port vmm to aarch64

Also prepare to drop VMM_FLAG_PRESENT on x86.

* protos: Port limine boot protocol to aarch64

Also drop VMM_FLAG_PRESENT since we never unmap pages anyway.

* test: Add DTB request

* PROTOCOL: Port SMP request to aarch64

* cpu: Add cache maintenance functions for aarch64

* protos/limine, sys: Port SMP to aarch64

Also move common asm macros into a header file.

* test: Start up APs

* vmm: Unify get_next_level and implement large page splitting

* protos/limine: Map framebuffer using correct caching mode on AArch64

* CI: Fix GCC build for aarch64

* entry, menu: Replace uses of naked attribute with separate asm file

GCC does not understand the naked attribute on aarch64, and didn't
understand it for x86 in older versions.
2022-08-18 17:32:54 +02:00
mintsuki
400202d926 misc: stage23 -> common 2022-02-03 10:38:43 +01:00