From edcdaa5c60fc8291dc29e8cb61ceee24d8ec05c1 Mon Sep 17 00:00:00 2001 From: kamkow1 Date: Mon, 17 Nov 2025 04:43:41 +0100 Subject: [PATCH] List PCI devices --- kernel/Makefile | 1 + kernel/kmain.c | 2 + kernel/pci/pci.c | 125 +++++++++++++++++++++++++++++++++++ kernel/pci/pci.h | 88 ++++++++++++++++++++++++ kernel/pci/reg.c | 113 +++++++++++++++++++++++++++++++ kernel/pci/reg.h | 169 +++++++++++++++++++++++++++++++++++++++++++++++ 6 files changed, 498 insertions(+) create mode 100644 kernel/pci/pci.c create mode 100644 kernel/pci/pci.h create mode 100644 kernel/pci/reg.c create mode 100644 kernel/pci/reg.h diff --git a/kernel/Makefile b/kernel/Makefile index f65ffc8..dede7e9 100644 --- a/kernel/Makefile +++ b/kernel/Makefile @@ -64,6 +64,7 @@ SRCFILES += $(call GRABSRC, \ intr \ cpu \ vmm \ + pci \ ) CFILES := $(call GET_CFILES, $(SRCFILES)) diff --git a/kernel/kmain.c b/kernel/kmain.c index d150194..18b65d7 100644 --- a/kernel/kmain.c +++ b/kernel/kmain.c @@ -18,6 +18,7 @@ #include "cpu/hang.h" #include "cpu/gdt.h" #include "ipc/mbus/mbus.h" +#include "pci/pci.h" void log_bootinfo(void) { char buf[100]; @@ -48,6 +49,7 @@ void kmain(void) { pmm_init(); vmm_init(); intr_init(); + pci_init(); randcrypto_init(); ipc_mbusinit(); dev_init(); diff --git a/kernel/pci/pci.c b/kernel/pci/pci.c new file mode 100644 index 0000000..d851c11 --- /dev/null +++ b/kernel/pci/pci.c @@ -0,0 +1,125 @@ +#include +#include +#include "pci/pci.h" +#include "pci/reg.h" +#include "io/io.h" +#include "std/string.h" +#include "util/util.h" +#include "kprintf.h" + +uint8_t pci_read8(uint32_t id, uint32_t reg) { + uint32_t addr = 0x80000000 | id | (reg & 0xFC); + io_out32(PCI_CONFIG_ADDR, addr); + return io_in8(PCI_CONFIG_DATA + (reg & 0x03)); +} + +uint16_t pci_read16(uint32_t id, uint32_t reg) { + uint32_t addr = 0x80000000 | id | (reg & 0xFC); + io_out32(PCI_CONFIG_ADDR, addr); + return io_in16(PCI_CONFIG_DATA + (reg & 0x02)); +} + +uint32_t pci_read32(uint32_t id, uint32_t reg) { + uint32_t addr = 0x80000000 | id | (reg & 0xFC); + io_out32(PCI_CONFIG_ADDR, addr); + return io_in32(PCI_CONFIG_DATA + reg); +} + +void pci_write8(uint32_t id, uint32_t reg, uint8_t v) { + uint32_t addr = 0x80000000 | id | (reg & 0xFC); + io_out32(PCI_CONFIG_ADDR, addr); + io_out8(PCI_CONFIG_DATA + (reg & 0x03), v); +} + +void pci_write16(uint32_t id, uint32_t reg, uint16_t v) { + uint32_t addr = 0x80000000 | id | (reg & 0xFC); + io_out32(PCI_CONFIG_ADDR, addr); + io_out16(PCI_CONFIG_DATA + (reg & 0x02), v); +} + +void pci_write32(uint32_t id, uint32_t reg, uint32_t v) { + uint32_t addr = 0x80000000 | id | (reg & 0xFC); + io_out32(PCI_CONFIG_ADDR, addr); + io_out32(PCI_CONFIG_DATA + reg, v); +} + +void pci_readbar(uint32_t id, uint32_t idx, uint32_t *addr, uint32_t *mask) { + uint32_t reg = PCI_BAR0 + idx * sizeof(uint32_t); + *addr = pci_read32(id, reg); + pci_write32(id, reg, 0xffffffff); + *mask = pci_read32(id, reg); + pci_write32(id, reg, *addr); +} + +void pci_getbar(PciBar *bar, uint32_t id, uint32_t idx) { + uint32_t addrlo; + uint32_t masklo; + pci_readbar(id, idx, &addrlo, &masklo); + + if (addrlo & PCI_BAR_MEM32) { + bar->u.addr = (void *)((uint64_t)(addrlo & ~0x3)); + bar->size = ~(masklo & ~0xF) + 1; + bar->flags = addrlo & 0xF; + } else if (addrlo & PCI_BAR_MEM64) { + uint32_t addrhi; + uint32_t maskhi; + pci_readbar(id, idx+1, &addrhi, &maskhi); + + bar->u.addr = (void *)(((uint64_t)addrhi << 32) | ((uint64_t)addrlo & ~0xF)); + bar->size = ~(((uint64_t)maskhi << 32) | ((uint64_t)masklo & ~0xF)) + 1; + bar->flags = addrlo & 0xF; + } else if (addrlo & PCI_BAR_IO) { + bar->u.port = (uint16_t)(addrlo & ~0x3); + bar->size = (uint16_t)(~(masklo & ~0x3) + 1); + bar->flags = addrlo & 0x3; + } +} + +static PciMatch PCI_MATCHES[] = { +}; + +void pci_visit(uint32_t bus, uint32_t dev, uint32_t fn) { + uint32_t id = PCI_MAKE_ID(bus, dev, fn); + + PciDevInfo devinfo; + memset(&devinfo, 0, sizeof(devinfo)); + + devinfo.vendorid = pci_read16(id, PCI_VENDORID); + if (devinfo.vendorid == 0xffff) { + return; + } + + devinfo.deviceid = pci_read16(id, PCI_DEVICEID); + devinfo.progintf = pci_read8(id, PCI_PROGINTF); + devinfo.subclass = pci_read8(id, PCI_SUBCLASS); + devinfo.classcode = pci_read8(id, PCI_CLASSCODE); + + devinfo.bus = bus; + devinfo.dev = dev; + devinfo.fn = fn; + + LOG("pci", "%02X:%02X:%u 0x%04X/0x%04X: %s\n", + bus, dev, fn, devinfo.vendorid, devinfo.deviceid, + pci_classname(devinfo.classcode, devinfo.subclass, devinfo.progintf)); + + for (size_t i = 0; i < LEN(PCI_MATCHES); i++) { + if ((PCI_MATCHES[i].k1 == devinfo.vendorid && PCI_MATCHES[i].k2 == devinfo.deviceid) + || (PCI_MATCHES[i].k1 == devinfo.classcode && PCI_MATCHES[i].k2 == devinfo.subclass)) { + PCI_MATCHES[i].initfn(&devinfo); + } + } +} + +void pci_init(void) { + for (uint32_t bus = 0; bus < 0x100; bus++) { + for (uint32_t dev = 0; dev < 32; dev++) { + uint32_t baseid = PCI_MAKE_ID(bus, dev, 0); + uint8_t hdrtype = pci_read8(baseid, PCI_HDRTYPE); + uint32_t fncount = hdrtype & PCI_MULTIFN ? 8 : 1; + + for (uint32_t fn = 0; fn < fncount; fn++) { + pci_visit(bus, dev, fn); + } + } + } +} diff --git a/kernel/pci/pci.h b/kernel/pci/pci.h new file mode 100644 index 0000000..1393859 --- /dev/null +++ b/kernel/pci/pci.h @@ -0,0 +1,88 @@ +#ifndef PCI_PCI_H_ +#define PCI_PCI_H_ + +#include +#include + +#define PCI_MAKE_ID(bus, dev, fn) (((bus)<<16) | ((dev)<<11) | ((fn)<<8)) + +#define PCI_CONFIG_ADDR 0xCF8 +#define PCI_CONFIG_DATA 0xCFC + +#define PCI_MULTIFN 0x80 +#define PCI_GENERIC 0x00 +#define PCI_PCI_BRIDGE 0x01 +#define PCI_CARDBUS_BRIDGE 0x02 + +#define PCI_VENDORID 0x00 +#define PCI_DEVICEID 0x02 +#define PCI_CMD 0x04 +#define PCI_STATUS 0x06 +#define PCI_REVID 0x08 +#define PCI_PROGINTF 0x09 +#define PCI_SUBCLASS 0x0A +#define PCI_CLASSCODE 0x0B +#define PCI_CACHELINESZ 0x0C +#define PCI_LATENCY 0x0D +#define PCI_HDRTYPE 0x0E +#define PCI_BIST 0x0F + +#define PCI_BAR0 0x10 +#define PCI_BAR1 0x14 +#define PCI_BAR2 0x18 +#define PCI_BAR3 0x1C +#define PCI_BAR4 0x20 +#define PCI_BAR5 0x24 +#define PCI_CARBUS_CIS 0x28 +#define PCI_SUBSYS_VENDORID 0x2C +#define PCI_SUBSYS_DEVICEID 0x2E +#define PCI_EXPROM 0x30 +#define PCI_CAP 0x34 +#define PCI_INTRLINE 0x3C +#define PCI_INTRPIN 0x3D +#define PCI_MIN_GRANT 0x3E +#define PCI_MAX_LATENCY 0x3F + +#define PCI_BAR_IO 0x01 +#define PCI_BAR_MEM32 0x02 +#define PCI_BAR_MEM64 0x04 +#define PCI_BAR_PREFETCH 0x08 + +typedef struct { + union { void *addr; uint16_t port; } u; + uint64_t size; + uint32_t flags; +} PciBar; + +typedef struct { + uint16_t vendorid; + uint16_t deviceid; + uint8_t classcode; + uint8_t subclass; + uint8_t progintf; + + uint32_t bus, dev, fn; +} PciDevInfo; + +typedef struct { + uint16_t k1; + uint16_t k2; + void (*initfn)(PciDevInfo *info); +} PciMatch; + +#define PCI_DEV_MAGIC 0xAB0BA + +typedef struct { + PciDevInfo devinfo; +} PciDev; + +uint8_t pci_read8(uint32_t id, uint32_t reg); +uint16_t pci_read16(uint32_t id, uint32_t reg); +uint32_t pci_read32(uint32_t id, uint32_t reg); +void pci_write8(uint32_t id, uint32_t reg, uint8_t v); +void pci_write16(uint32_t id, uint32_t reg, uint16_t v); +void pci_write32(uint32_t id, uint32_t reg, uint32_t v); + +void pci_init(void); + +#endif // PCI_PCI_H_ diff --git a/kernel/pci/reg.c b/kernel/pci/reg.c new file mode 100644 index 0000000..7d304db --- /dev/null +++ b/kernel/pci/reg.c @@ -0,0 +1,113 @@ +#include +#include +#include "pci/reg.h" + +const char *pci_devname(uint32_t vendorid, uint32_t deviceid) { + return "Unknown Device"; +} + +const char *pci_classname(uint32_t classcode, uint32_t subclass, uint32_t progintf) { + switch ((classcode << 8) | subclass) + { + case PCI_VGA_COMPATIBLE: return "VGA-Compatible Device"; + case PCI_STORAGE_SCSI: return "SCSI Storage Controller"; + case PCI_STORAGE_IDE: return "IDE Interface"; + case PCI_STORAGE_FLOPPY: return "Floppy Disk Controller"; + case PCI_STORAGE_IPI: return "IPI Bus Controller"; + case PCI_STORAGE_RAID: return "RAID Bus Controller"; + case PCI_STORAGE_ATA: return "ATA Controller"; + case PCI_STORAGE_SATA: return "SATA Controller"; + case PCI_STORAGE_OTHER: return "Mass Storage Controller"; + case PCI_NETWORK_ETHERNET: return "Ethernet Controller"; + case PCI_NETWORK_TOKEN_RING: return "Token Ring Controller"; + case PCI_NETWORK_FDDI: return "FDDI Controller"; + case PCI_NETWORK_ATM: return "ATM Controller"; + case PCI_NETWORK_ISDN: return "ISDN Controller"; + case PCI_NETWORK_WORLDFIP: return "WorldFip Controller"; + case PCI_NETWORK_PICGMG: return "PICMG Controller"; + case PCI_NETWORK_OTHER: return "Network Controller"; + case PCI_DISPLAY_VGA: return "VGA-Compatible Controller"; + case PCI_DISPLAY_XGA: return "XGA-Compatible Controller"; + case PCI_DISPLAY_3D: return "3D Controller"; + case PCI_DISPLAY_OTHER: return "Display Controller"; + case PCI_MULTIMEDIA_VIDEO: return "Multimedia Video Controller"; + case PCI_MULTIMEDIA_AUDIO: return "Multimedia Audio Controller"; + case PCI_MULTIMEDIA_PHONE: return "Computer Telephony Device"; + case PCI_MULTIMEDIA_AUDIO_DEVICE: return "Audio Device"; + case PCI_MULTIMEDIA_OTHER: return "Multimedia Controller"; + case PCI_MEMORY_RAM: return "RAM Memory"; + case PCI_MEMORY_FLASH: return "Flash Memory"; + case PCI_MEMORY_OTHER: return "Memory Controller"; + case PCI_BRIDGE_HOST: return "Host Bridge"; + case PCI_BRIDGE_ISA: return "ISA Bridge"; + case PCI_BRIDGE_EISA: return "EISA Bridge"; + case PCI_BRIDGE_MCA: return "MicroChannel Bridge"; + case PCI_BRIDGE_PCI: return "PCI Bridge"; + case PCI_BRIDGE_PCMCIA: return "PCMCIA Bridge"; + case PCI_BRIDGE_NUBUS: return "NuBus Bridge"; + case PCI_BRIDGE_CARDBUS: return "CardBus Bridge"; + case PCI_BRIDGE_RACEWAY: return "RACEway Bridge"; + case PCI_BRIDGE_OTHER: return "Bridge Device"; + case PCI_COMM_SERIAL: return "Serial Controller"; + case PCI_COMM_PARALLEL: return "Parallel Controller"; + case PCI_COMM_MULTIPORT: return "Multiport Serial Controller"; + case PCI_COMM_MODEM: return "Modem"; + case PCI_COMM_OTHER: return "Communication Controller"; + case PCI_SYSTEM_PIC: return "PIC"; + case PCI_SYSTEM_DMA: return "DMA Controller"; + case PCI_SYSTEM_TIMER: return "Timer"; + case PCI_SYSTEM_RTC: return "RTC"; + case PCI_SYSTEM_PCI_HOTPLUG: return "PCI Hot-Plug Controller"; + case PCI_SYSTEM_SD: return "SD Host Controller"; + case PCI_SYSTEM_OTHER: return "System Peripheral"; + case PCI_INPUT_KEYBOARD: return "Keyboard Controller"; + case PCI_INPUT_PEN: return "Pen Controller"; + case PCI_INPUT_MOUSE: return "Mouse Controller"; + case PCI_INPUT_SCANNER: return "Scanner Controller"; + case PCI_INPUT_GAMEPORT: return "Gameport Controller"; + case PCI_INPUT_OTHER: return "Input Controller"; + case PCI_DOCKING_GENERIC: return "Generic Docking Station"; + case PCI_DOCKING_OTHER: return "Docking Station"; + case PCI_PROCESSOR_386: return "386"; + case PCI_PROCESSOR_486: return "486"; + case PCI_PROCESSOR_PENTIUM: return "Pentium"; + case PCI_PROCESSOR_ALPHA: return "Alpha"; + case PCI_PROCESSOR_MIPS: return "MIPS"; + case PCI_PROCESSOR_CO: return "CO-Processor"; + case PCI_SERIAL_FIREWIRE: return "FireWire (IEEE 1394)"; + case PCI_SERIAL_SSA: return "SSA"; + case PCI_SERIAL_USB: + switch (progintf) + { + case PCI_SERIAL_USB_UHCI: return "USB (UHCI)"; + case PCI_SERIAL_USB_OHCI: return "USB (OHCI)"; + case PCI_SERIAL_USB_EHCI: return "USB2"; + case PCI_SERIAL_USB_XHCI: return "USB3"; + case PCI_SERIAL_USB_OTHER: return "USB Controller"; + default: return "Unknown USB Class"; + } + break; + case PCI_SERIAL_FIBER: return "Fiber Channel"; + case PCI_SERIAL_SMBUS: return "SMBus"; + case PCI_WIRELESS_IRDA: return "iRDA Compatible Controller"; + case PCI_WIRLESSS_IR: return "Consumer IR Controller"; + case PCI_WIRLESSS_RF: return "RF Controller"; + case PCI_WIRLESSS_BLUETOOTH: return "Bluetooth"; + case PCI_WIRLESSS_BROADBAND: return "Broadband"; + case PCI_WIRLESSS_ETHERNET_A: return "802.1a Controller"; + case PCI_WIRLESSS_ETHERNET_B: return "802.1b Controller"; + case PCI_WIRELESS_OTHER: return "Wireless Controller"; + case PCI_INTELLIGENT_I2O: return "I2O Controller"; + case PCI_SATELLITE_TV: return "Satellite TV Controller"; + case PCI_SATELLITE_AUDIO: return "Satellite Audio Controller"; + case PCI_SATELLITE_VOICE: return "Satellite Voice Controller"; + case PCI_SATELLITE_DATA: return "Satellite Data Controller"; + case PCI_CRYPT_NETWORK: return "Network and Computing Encryption Device"; + case PCI_CRYPT_ENTERTAINMENT: return "Entertainment Encryption Device"; + case PCI_CRYPT_OTHER: return "Encryption Device"; + case PCI_SP_DPIO: return "DPIO Modules"; + case PCI_SP_OTHER: return "Signal Processing Controller"; + } + + return "Unknown PCI Class"; +} diff --git a/kernel/pci/reg.h b/kernel/pci/reg.h new file mode 100644 index 0000000..a9173b1 --- /dev/null +++ b/kernel/pci/reg.h @@ -0,0 +1,169 @@ +#ifndef PCI_REG_H_ +#define PCI_REG_H_ + +#include +#include + +// PCI Vendors +#define PCI_VENDOR_INTEL 0x8086 + +// PCI Classes +#define PCI_CLASS_LEGACY 0x00 +#define PCI_CLASS_STORAGE 0x01 +#define PCI_CLASS_NETWORK 0x02 +#define PCI_CLASS_DISPLAY 0x03 +#define PCI_CLASS_MULTIMEDIA 0x04 +#define PCI_CLASS_MEMORY 0x05 +#define PCI_CLASS_BRIDGE_DEVICE 0x06 +#define PCI_CLASS_COMMUNICATION 0x07 +#define PCI_CLASS_PERIHPERALS 0x08 +#define PCI_CLASS_INPUT_DEVICES 0x09 +#define PCI_CLASS_DOCKING_STATION 0x0a +#define PCI_CLASS_PROCESSOR 0x0b +#define PCI_CLASS_SERIAL_BUS 0x0c +#define PCI_CLASS_WIRELESS 0x0d +#define PCI_CLASS_INTELLIGENT_IO 0x0e +#define PCI_CLASS_SATELLITE 0x0f +#define PCI_CLASS_CRYPT 0x10 +#define PCI_CLASS_SIGNAL_PROCESSING 0x11 +#define PCI_CLASS_UNDEFINED 0xff + +// Undefined Class +#define PCI_UNCLASSIFIED 0x0000 +#define PCI_VGA_COMPATIBLE 0x0001 + +// Mass Storage Controller +#define PCI_STORAGE_SCSI 0x0100 +#define PCI_STORAGE_IDE 0x0101 +#define PCI_STORAGE_FLOPPY 0x0102 +#define PCI_STORAGE_IPI 0x0103 +#define PCI_STORAGE_RAID 0x0104 +#define PCI_STORAGE_ATA 0x0105 +#define PCI_STORAGE_SATA 0x0106 +#define PCI_STORAGE_OTHER 0x0180 + +// Network Controller +#define PCI_NETWORK_ETHERNET 0x0200 +#define PCI_NETWORK_TOKEN_RING 0x0201 +#define PCI_NETWORK_FDDI 0x0202 +#define PCI_NETWORK_ATM 0x0203 +#define PCI_NETWORK_ISDN 0x0204 +#define PCI_NETWORK_WORLDFIP 0x0205 +#define PCI_NETWORK_PICGMG 0x0206 +#define PCI_NETWORK_OTHER 0x0280 + +// Display Controller +#define PCI_DISPLAY_VGA 0x0300 +#define PCI_DISPLAY_XGA 0x0301 +#define PCI_DISPLAY_3D 0x0302 +#define PCI_DISPLAY_OTHER 0x0380 + +// Multimedia Controller +#define PCI_MULTIMEDIA_VIDEO 0x0400 +#define PCI_MULTIMEDIA_AUDIO 0x0401 +#define PCI_MULTIMEDIA_PHONE 0x0402 +#define PCI_MULTIMEDIA_AUDIO_DEVICE 0x0403 +#define PCI_MULTIMEDIA_OTHER 0x0480 + +// Memory Controller +#define PCI_MEMORY_RAM 0x0500 +#define PCI_MEMORY_FLASH 0x0501 +#define PCI_MEMORY_OTHER 0x0580 + +// Bridge Device +#define PCI_BRIDGE_HOST 0x0600 +#define PCI_BRIDGE_ISA 0x0601 +#define PCI_BRIDGE_EISA 0x0602 +#define PCI_BRIDGE_MCA 0x0603 +#define PCI_BRIDGE_PCI 0x0604 +#define PCI_BRIDGE_PCMCIA 0x0605 +#define PCI_BRIDGE_NUBUS 0x0606 +#define PCI_BRIDGE_CARDBUS 0x0607 +#define PCI_BRIDGE_RACEWAY 0x0608 +#define PCI_BRIDGE_OTHER 0x0680 + +// Simple Communication Controller +#define PCI_COMM_SERIAL 0x0700 +#define PCI_COMM_PARALLEL 0x0701 +#define PCI_COMM_MULTIPORT 0x0702 +#define PCI_COMM_MODEM 0x0703 +#define PCI_COMM_GPIB 0x0704 +#define PCI_COMM_SMARTCARD 0x0705 +#define PCI_COMM_OTHER 0x0780 + +// Base System Peripherals +#define PCI_SYSTEM_PIC 0x0800 +#define PCI_SYSTEM_DMA 0x0801 +#define PCI_SYSTEM_TIMER 0x0802 +#define PCI_SYSTEM_RTC 0x0803 +#define PCI_SYSTEM_PCI_HOTPLUG 0x0804 +#define PCI_SYSTEM_SD 0x0805 +#define PCI_SYSTEM_OTHER 0x0880 + +// Input Devices +#define PCI_INPUT_KEYBOARD 0x0900 +#define PCI_INPUT_PEN 0x0901 +#define PCI_INPUT_MOUSE 0x0902 +#define PCI_INPUT_SCANNER 0x0903 +#define PCI_INPUT_GAMEPORT 0x0904 +#define PCI_INPUT_OTHER 0x0980 + +// Docking Stations +#define PCI_DOCKING_GENERIC 0x0a00 +#define PCI_DOCKING_OTHER 0x0a80 + +// Processors +#define PCI_PROCESSOR_386 0x0b00 +#define PCI_PROCESSOR_486 0x0b01 +#define PCI_PROCESSOR_PENTIUM 0x0b02 +#define PCI_PROCESSOR_ALPHA 0x0b10 +#define PCI_PROCESSOR_POWERPC 0x0b20 +#define PCI_PROCESSOR_MIPS 0x0b30 +#define PCI_PROCESSOR_CO 0x0b40 + +// Serial Bus Controllers +#define PCI_SERIAL_FIREWIRE 0x0c00 +#define PCI_SERIAL_ACCESS 0x0c01 +#define PCI_SERIAL_SSA 0x0c02 +#define PCI_SERIAL_USB 0x0c03 +#define PCI_SERIAL_FIBER 0x0c04 +#define PCI_SERIAL_SMBUS 0x0c05 + +#define PCI_SERIAL_USB_UHCI 0x00 +#define PCI_SERIAL_USB_OHCI 0x10 +#define PCI_SERIAL_USB_EHCI 0x20 +#define PCI_SERIAL_USB_XHCI 0x30 +#define PCI_SERIAL_USB_OTHER 0x80 + +// Wireless Controllers +#define PCI_WIRELESS_IRDA 0x0d00 +#define PCI_WIRLESSS_IR 0x0d01 +#define PCI_WIRLESSS_RF 0x0d10 +#define PCI_WIRLESSS_BLUETOOTH 0x0d11 +#define PCI_WIRLESSS_BROADBAND 0x0d12 +#define PCI_WIRLESSS_ETHERNET_A 0x0d20 +#define PCI_WIRLESSS_ETHERNET_B 0x0d21 +#define PCI_WIRELESS_OTHER 0x0d80 + +// Intelligent I/O Controllers +#define PCI_INTELLIGENT_I2O 0x0e00 + +// Satellite Communication Controllers +#define PCI_SATELLITE_TV 0x0f00 +#define PCI_SATELLITE_AUDIO 0x0f01 +#define PCI_SATELLITE_VOICE 0x0f03 +#define PCI_SATELLITE_DATA 0x0f04 + +// Encryption/Decryption Controllers +#define PCI_CRYPT_NETWORK 0x1000 +#define PCI_CRYPT_ENTERTAINMENT 0x1001 +#define PCI_CRYPT_OTHER 0x1080 + +// Data Acquisition and Signal Processing Controllers +#define PCI_SP_DPIO 0x1100 +#define PCI_SP_OTHER 0x1180 + +const char *pci_devname(uint32_t vendorid, uint32_t deviceid); +const char *pci_classname(uint32_t classcode, uint32_t subclass, uint32_t progintf); + +#endif // PCI_REG_H_