Implement interrupts

2025-08-19 22:51:33 +02:00
parent 92ccd189e7
commit 3f6df79885
14 changed files with 455 additions and 101 deletions
--- a/kernel/hal/x86_64/isr0.S
+++ b/kernel/hal/x86_64/isr0.S
@ -0,0 +1,175 @@
+.extern isr_handleintr
+
+.global isr_vec0
+.global isr_vec1
+.global isr_vec2
+.global isr_vec3
+.global isr_vec4
+.global isr_vec5
+.global isr_vec6
+.global isr_vec7
+.global isr_vec8
+.global isr_vec10
+.global isr_vec11
+.global isr_vec12
+.global isr_vec13
+.global isr_vec14
+.global isr_vec16
+.global isr_vec17
+.global isr_vec18
+.global isr_vec19
+.global isr_vec20
+.global isr_vec21
+.global isr_vec32
+.global isr_vec33
+.global isr_vec39
+
+.macro _PUSHAQ
+  push %rax
+  push %rbx
+  push %rcx
+  push %rdx
+  push %rbp
+  push %rdi
+  push %rsi
+  push %r8
+  push %r9
+  push %r10
+  push %r11
+  push %r12
+  push %r13
+  push %r14
+  push %r15
+.endm
+
+.macro _POPAQ
+  pop %r15
+  pop %r14
+  pop %r13
+  pop %r12
+  pop %r11
+  pop %r10
+  pop %r9
+  pop %r8
+  pop %rsi
+  pop %rdi
+  pop %rbp
+  pop %rdx
+  pop %rcx
+  pop %rbx
+  pop %rax
+.endm
+
+.macro _PUSHACR
+  mov %cr0, %rax
+  push %rax
+
+  mov %cr2, %rax
+  push %rax
+
+  mov %cr3, %rax
+  push %rax
+
+  mov %cr4, %rax
+  push %rax
+
+  mov %cr8, %rax
+  push %rax
+.endm
+
+.macro _vecintr_errorcode_present_save num
+  push $\num
+  _PUSHAQ
+  _PUSHACR
+.endm
+
+.macro _vecintr_plain_save num errorno
+  push $\errorno
+  push $\num
+  _PUSHAQ
+  _PUSHACR
+.endm
+
+.macro _vecintr_restore
+  add 40, %rsp
+  _POPAQ
+  add 16, %rsp
+.endm
+
+.macro _vecintr_bodygen
+  cld
+  mov %rsp, %rdi
+  call isr_handleintr
+  _vecintr_restore
+  iretq
+.endm
+
+isr_vec0:
+  _vecintr_plain_save 0, 0
+  _vecintr_bodygen
+isr_vec1:
+  _vecintr_plain_save 1, 0
+  _vecintr_bodygen
+isr_vec2:
+  _vecintr_plain_save 2, 0
+  _vecintr_bodygen
+isr_vec3:
+  _vecintr_plain_save 3, 0
+  _vecintr_bodygen
+isr_vec4:
+  _vecintr_plain_save 4, 0
+  _vecintr_bodygen
+isr_vec5:
+  _vecintr_plain_save 5, 0
+  _vecintr_bodygen
+isr_vec6:
+  _vecintr_plain_save 6, 0
+  _vecintr_bodygen
+isr_vec7:
+  _vecintr_plain_save 7, 0
+  _vecintr_bodygen
+isr_vec8:
+  _vecintr_errorcode_present_save 8
+  _vecintr_bodygen
+isr_vec10:
+  _vecintr_errorcode_present_save 10
+  _vecintr_bodygen
+isr_vec11:
+  _vecintr_errorcode_present_save 11
+  _vecintr_bodygen
+isr_vec12:
+  _vecintr_errorcode_present_save 12
+  _vecintr_bodygen
+isr_vec13:
+  _vecintr_errorcode_present_save 13
+  _vecintr_bodygen
+isr_vec14:
+  _vecintr_errorcode_present_save 14
+  _vecintr_bodygen
+isr_vec16:
+  _vecintr_plain_save 16, 0
+  _vecintr_bodygen
+isr_vec17:
+  _vecintr_errorcode_present_save 17
+  _vecintr_bodygen
+isr_vec18:
+  _vecintr_plain_save 18, 0
+  _vecintr_bodygen
+isr_vec19:
+  _vecintr_plain_save 19, 0
+  _vecintr_bodygen
+isr_vec20:
+  _vecintr_plain_save 20, 0
+  _vecintr_bodygen
+isr_vec21:
+  _vecintr_errorcode_present_save 21
+  _vecintr_bodygen
+isr_vec32:
+  _vecintr_plain_save 32, 0
+  _vecintr_bodygen
+isr_vec33:
+  _vecintr_plain_save 33, 0
+  _vecintr_bodygen
+isr_vec39:
+  _vecintr_plain_save 39, 0
+  _vecintr_bodygen