235 lines
7.3 KiB
C
235 lines
7.3 KiB
C
#include <amd64/apic.h>
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#include <amd64/intr_defs.h>
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#include <amd64/msr-index.h>
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#include <amd64/msr.h>
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#include <libk/std.h>
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#include <limine/requests.h>
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#include <sys/debug.h>
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#include <sys/mm.h>
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#include <sys/time.h>
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#include <uacpi/acpi.h>
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#include <uacpi/status.h>
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#include <uacpi/tables.h>
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#include <uacpi/uacpi.h>
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#define IOAPICS_MAX 24
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#define INTERRUPT_SRC_OVERRIDES_MAX 24
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#define LAPIC_ID 0x20 /* ID */
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#define LAPIC_EOI 0xB0 /* End of interrupt */
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#define LAPIC_SIVR 0xF0 /* Spurious interrupt vector register */
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#define LAPIC_ICR 0x300 /* Interrupt command register */
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#define LAPIC_LVTTR 0x320 /* LVT timer register */
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#define LAPIC_TIMICT 0x380 /* Initial count register */
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#define LAPIC_TIMCCT 0x390 /* Current count register */
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#define LAPIC_DCR 0x3E0 /* Divide config register */
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static struct acpi_madt_ioapic apics[IOAPICS_MAX];
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/* clang-format off */
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static struct acpi_madt_interrupt_source_override intr_src_overrides[INTERRUPT_SRC_OVERRIDES_MAX];
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/* clang-format on */
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static size_t ioapic_entries = 0;
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static size_t intr_src_override_entries = 0;
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static uintptr_t lapic_mmio_base = 0;
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extern void amd64_spin (void);
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static uint32_t amd64_ioapic_read (uintptr_t vaddr, uint32_t reg) {
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*(volatile uint32_t*)vaddr = reg;
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return *(volatile uint32_t*)(vaddr + 0x10);
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}
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static void amd64_ioapic_write (uintptr_t vaddr, uint32_t reg, uint32_t value) {
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*(volatile uint32_t*)vaddr = reg;
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*(volatile uint32_t*)(vaddr + 0x10) = value;
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}
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static struct acpi_madt_ioapic* amd64_ioapic_find (uint8_t irq) {
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struct acpi_madt_ioapic* apic = NULL;
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struct limine_hhdm_response* hhdm = limine_hhdm_request.response;
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for (size_t i = 0; i < ioapic_entries; i++) {
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apic = &apics[i];
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uint32_t version = amd64_ioapic_read ((uintptr_t)hhdm->offset + (uintptr_t)apic->address, 1);
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uint32_t max = ((version >> 16) & 0xFF);
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if ((irq >= apic->gsi_base) && (irq <= (apic->gsi_base + max)))
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return apic;
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}
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return NULL;
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}
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void amd64_ioapic_route_irq (uint8_t vec, uint8_t irq, uint64_t flags, uint64_t lapic_id) {
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struct acpi_madt_ioapic* apic = NULL;
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struct acpi_madt_interrupt_source_override* override;
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bool found_override = false;
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struct limine_hhdm_response* hhdm = limine_hhdm_request.response;
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for (size_t i = 0; i < intr_src_override_entries; i++) {
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override = &intr_src_overrides[i];
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if (override->source == irq) {
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found_override = true;
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break;
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}
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}
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uint64_t calc_flags = (lapic_id << 56) | (flags) | (vec & 0xFF);
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if (found_override) {
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uint8_t polarity = ((override->flags & 0x03) == 0x03) ? 1 : 0;
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uint8_t mode = (((override->flags >> 2) & 0x03) == 0x03) ? 1 : 0;
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calc_flags |= (uint64_t)mode << 15;
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calc_flags |= (uint64_t)polarity << 13;
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calc_flags |= flags;
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} else {
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calc_flags |= flags;
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}
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apic = amd64_ioapic_find (irq);
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if (apic == NULL)
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return;
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uint32_t irq_reg = ((irq - apic->gsi_base) * 2) + 0x10;
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amd64_ioapic_write ((uintptr_t)hhdm->offset + (uintptr_t)apic->address, irq_reg,
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(uint32_t)calc_flags);
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amd64_ioapic_write ((uintptr_t)hhdm->offset + (uintptr_t)apic->address, irq_reg + 1,
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(uint32_t)(calc_flags >> 32));
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}
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void amd64_ioapic_mask (uint8_t irq) {
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struct acpi_madt_ioapic* apic;
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struct limine_hhdm_response* hhdm = limine_hhdm_request.response;
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apic = amd64_ioapic_find (irq);
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if (apic == NULL)
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return;
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uint32_t irq_reg = ((irq - apic->gsi_base) * 2) + 0x10;
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uint32_t value = amd64_ioapic_read ((uintptr_t)hhdm->offset + (uintptr_t)apic->address, irq_reg);
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amd64_ioapic_write ((uintptr_t)hhdm->offset + (uintptr_t)apic->address, irq_reg,
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value | (1 << 16));
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}
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void amd64_ioapic_unmask (uint8_t irq) {
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struct acpi_madt_ioapic* apic;
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struct limine_hhdm_response* hhdm = limine_hhdm_request.response;
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apic = amd64_ioapic_find (irq);
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if (apic == NULL)
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return;
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uint32_t irq_reg = ((irq - apic->gsi_base) * 2) + 0x10;
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uint32_t value = amd64_ioapic_read ((uintptr_t)hhdm->offset + (uintptr_t)apic->address, irq_reg);
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amd64_ioapic_write ((uintptr_t)hhdm->offset + (uintptr_t)apic->address, irq_reg,
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value & ~(1 << 16));
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}
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void amd64_ioapic_init (void) {
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struct limine_hhdm_response* hhdm = limine_hhdm_request.response;
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struct uacpi_table apic_table;
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uacpi_status status = uacpi_table_find_by_signature (ACPI_MADT_SIGNATURE, &apic_table);
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if (status != UACPI_STATUS_OK) {
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DEBUG ("Could not find MADT table!\n");
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amd64_spin ();
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}
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struct acpi_madt* apic = (struct acpi_madt*)apic_table.virt_addr;
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struct acpi_entry_hdr* current = (struct acpi_entry_hdr*)apic->entries;
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for (;;) {
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if ((uintptr_t)current >=
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((uintptr_t)apic->entries + apic->hdr.length - sizeof (struct acpi_madt)))
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break;
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switch (current->type) {
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case ACPI_MADT_ENTRY_TYPE_IOAPIC: {
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struct acpi_madt_ioapic* ioapic = (struct acpi_madt_ioapic*)current;
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mm_map_kernel_page ((uintptr_t)ioapic->address,
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(uintptr_t)hhdm->offset + (uintptr_t)ioapic->address,
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MM_PG_PRESENT | MM_PG_RW | MM_PD_RELOAD);
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apics[ioapic_entries++] = *ioapic;
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} break;
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case ACPI_MADT_ENTRY_TYPE_INTERRUPT_SOURCE_OVERRIDE: {
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struct acpi_madt_interrupt_source_override* override =
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(struct acpi_madt_interrupt_source_override*)current;
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intr_src_overrides[intr_src_override_entries++] = *override;
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} break;
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}
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current = (struct acpi_entry_hdr*)((uintptr_t)current + current->length);
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}
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}
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static uintptr_t amd64_lapic_base (void) { return lapic_mmio_base; }
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static void amd64_lapic_write (uint32_t reg, uint32_t value) {
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*(volatile uint32_t*)(amd64_lapic_base () + reg) = value;
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}
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static uint32_t amd64_lapic_read (uint32_t reg) {
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return *(volatile uint32_t*)(amd64_lapic_base () + reg);
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}
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uint32_t amd64_lapic_id (void) { return amd64_lapic_read (LAPIC_ID) >> 24; }
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void amd64_lapic_eoi (void) { amd64_lapic_write (LAPIC_EOI, 0); }
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void amd64_lapic_tick (uint32_t tick) { amd64_lapic_write (LAPIC_TIMICT, tick); }
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static uint32_t amd64_lapic_calibrate (uint32_t us) {
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amd64_lapic_write (LAPIC_DCR, 0x03);
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amd64_lapic_write (LAPIC_LVTTR, SCHED_PREEMPT_TIMER | (1 << 16));
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amd64_lapic_write (LAPIC_TIMICT, 0xFFFFFFFF);
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sleep_micro (us);
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uint32_t ticks = 0xFFFFFFFF - amd64_lapic_read (LAPIC_TIMCCT);
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return ticks;
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}
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static void amd64_lapic_start (uint32_t ticks) {
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amd64_lapic_write (LAPIC_DCR, 0x03);
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amd64_lapic_write (LAPIC_LVTTR, SCHED_PREEMPT_TIMER | (1 << 17));
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amd64_lapic_write (LAPIC_TIMICT, ticks);
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}
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uint64_t amd64_lapic_init (uint32_t us) {
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struct limine_hhdm_response* hhdm = limine_hhdm_request.response;
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amd64_wrmsr (MSR_APIC_BASE, amd64_rdmsr (MSR_APIC_BASE) | (1 << 11));
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uintptr_t lapic_paddr = amd64_rdmsr (MSR_APIC_BASE) & 0xFFFFF000;
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lapic_mmio_base = lapic_paddr + (uintptr_t)hhdm->offset;
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mm_map_kernel_page (lapic_paddr, lapic_mmio_base,
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MM_PG_PRESENT | MM_PG_RW | MM_PD_LOCK | MM_PD_RELOAD);
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amd64_lapic_write (LAPIC_SIVR, 0xFF | (1 << 8));
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uint32_t ticks = amd64_lapic_calibrate (us);
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amd64_lapic_start (ticks);
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return ticks;
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}
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void amd64_lapic_ipi (uint8_t lapic_id, uint8_t vec) {
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amd64_lapic_write (LAPIC_ICR + 0x10, (lapic_id << 24));
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amd64_lapic_write (LAPIC_ICR, vec);
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}
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