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mop3/kernel/device/pci/pci.h
kamkow1 a2ed5c2b8a
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idedrv Implement DMA reading/writing without IRQ support
2026-04-26 18:47:05 +02:00

105 lines
2.8 KiB
C

#ifndef _KERNEL_DEVICE_PCI_H
#define _KERNEL_DEVICE_PCI_H
#include <device/pci/pci_info.h>
#include <libk/std.h>
#include <proc/proc.h>
#include <proc/reschedule.h>
#define PCI_CONFIG_ADDR 0xCF8
#define PCI_CONFIG_DATA 0xCFC
#define PCI_VENDOR_ID 0x00
#define PCI_DEVICE_ID 0x02
#define PCI_COMMAND 0x04
#define PCI_STATUS 0x06
#define PCI_REVISION_ID 0x08
#define PCI_PROG_IF 0x09
#define PCI_SUBCLASS 0x0A
#define PCI_CLASS 0x0B
#define PCI_CACHELINE 0x0C
#define PCI_LATENCY 0x0D
#define PCI_HEADER_TYPE 0x0E
#define PCI_BIST 0x0F
#define PCI_BAR0 0x10
#define PCI_BAR1 0x14
#define PCI_BAR2 0x18
#define PCI_BAR3 0x1C
#define PCI_BAR4 0x20
#define PCI_BAR5 0x24
#define PCI_CAPABILITY 0x34
#define PCI_INTERRUPT_LINE 0x3C
#define PCI_INTERRUPT_PIN 0x3D
#define PCI_BAR_IO 0x01
#define PCI_BAR_MEM32 0x02
#define PCI_BAR_MEM64 0x04
#define PCI_BAR_PREFETCH 0x08
#define PCI_CMD_IOSPACE 0
#define PCI_CMD_MEMSPACE 1
#define PCI_CMD_BUSMASTER 2
#define PCI_CMD_SPECIAL_CYCLES 3
#define PCI_CMD_MEMWRIVENA 4
#define PCI_CMD_VGA_PALT_SNOOP 5
#define PCI_CMD_PARITY_ERR_RESP 6
#define PCI_CMD_SERR 8
#define PCI_CMD_FBBENA 9
#define PCI_CMD_INTRDISABLE 10
#define PCI_CAP_MSI 0x05
struct pci_vendor {
uint16_t id;
const char* name;
};
struct pci_device_id {
uint16_t vendor_id;
uint16_t device_id;
const char* name;
};
struct pci_class {
uint8_t class;
uint8_t subclass;
const char* name;
};
struct pci_driver_info {
uint8_t class;
uint8_t subclass;
bool (*init)(struct proc* proc, struct reschedule_ctx* rctx, struct pci_info pci_info);
};
typedef void (*pci_cb_func_t)(struct proc* proc, struct reschedule_ctx* rctx,
struct pci_info pci_info);
void pci_init(void);
uint32_t pci_read32(uint8_t bus, uint8_t slot, uint8_t func, uint8_t offset);
void pci_write32(uint8_t bus, uint8_t slot, uint8_t func, uint8_t offset, uint32_t value);
uint16_t pci_read16(uint8_t bus, uint8_t slot, uint8_t func, uint8_t offset);
void pci_write16(uint8_t bus, uint8_t slot, uint8_t func, uint8_t offset, uint16_t value);
uint8_t pci_read8(uint8_t bus, uint8_t slot, uint8_t func, uint8_t offset);
void pci_write8(uint8_t bus, uint8_t slot, uint8_t func, uint8_t offset, uint8_t value);
uint8_t pci_find_cap(uint8_t bus, uint8_t slot, uint8_t func, uint8_t cap_id);
bool pci_msi_init(uint8_t bus, uint8_t slot, uint8_t func, uint8_t vec, uint32_t lapic_id);
uint64_t pci_get_bar_size(uint8_t bus, uint8_t slot, uint8_t func, uint8_t bar_offset);
extern const struct pci_vendor pci_vendors[];
extern const struct pci_device_id pci_device_names[];
extern const struct pci_class pci_classes[];
#endif // _KERNEL_DEVICE_PCI_H