115 lines
3.2 KiB
C
115 lines
3.2 KiB
C
#include <amd64/apic.h>
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#include <amd64/intr_defs.h>
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#include <device/def_device_op.h>
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#include <device/device.h>
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#include <device/pci/pci.h>
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#include <device/pci/pci_info.h>
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#include <device/pci/pci_xhci.h>
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#include <device/usb/xhci.h>
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#include <devices.h>
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#include <libk/align.h>
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#include <libk/lengthof.h>
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#include <libk/printf.h>
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#include <libk/std.h>
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#include <limine/requests.h>
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#include <proc/proc.h>
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#include <proc/reschedule.h>
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#include <sys/debug.h>
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#include <sys/mm.h>
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static bool xhci_init_done = false;
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bool pci_xhci_init(struct proc* proc, struct reschedule_ctx* rctx, struct pci_info pci_info) {
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struct limine_hhdm_response* hhdm = limine_hhdm_request.response;
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uint8_t progif = pci_read8(pci_info.bus, pci_info.slot, pci_info.func, PCI_PROG_IF);
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/* not an XHCI controller */
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if (progif != 0x30) {
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return true;
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}
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if (xhci_init_done) {
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DEBUG("Cannot initialize more XHCI controllers\n");
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return false;
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}
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uint16_t pci_cmd = pci_read16(pci_info.bus, pci_info.slot, pci_info.func, PCI_COMMAND);
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uint16_t new_cmd = pci_cmd;
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new_cmd |= (1 << PCI_CMD_MEMSPACE);
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new_cmd |= (1 << PCI_CMD_BUSMASTER);
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new_cmd &= ~(1 << PCI_CMD_INTRDISABLE);
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if (pci_cmd != new_cmd) {
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pci_write16(pci_info.bus, pci_info.slot, pci_info.func, PCI_COMMAND, new_cmd);
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}
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uintptr_t xhci_phys = 0;
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size_t map_pages = 0;
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uint32_t bar0 = pci_read32(pci_info.bus, pci_info.slot, pci_info.func, PCI_BAR0);
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map_pages = pci_get_bar_size(pci_info.bus, pci_info.slot, pci_info.func, PCI_BAR0);
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map_pages = div_align_up(map_pages, PAGE_SIZE);
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if ((bar0 & 0x6) == 0x4) {
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uint32_t bar1 = pci_read32(pci_info.bus, pci_info.slot, pci_info.func, PCI_BAR1);
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xhci_phys = ((uint64_t)bar1 << 32) | (bar0 & ~0xF);
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DEBUG("XHCI phys base addr=%p (64 bit)\n", xhci_phys);
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} else {
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xhci_phys = (bar0 & ~0xF);
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DEBUG("XHCI phys base addr=%p (32 bit)\n", xhci_phys);
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}
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if (xhci_phys == 0) {
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DEBUG("WARNING xhci_phys is NULL!\n");
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return false;
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}
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uintptr_t xhci_base = xhci_phys + (uintptr_t)hhdm->offset;
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DEBUG("BAR size = %zu pages\n", map_pages);
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for (size_t page = 0; page < map_pages; page++) {
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mm_map_kernel_page(xhci_phys + page * PAGE_SIZE, xhci_base + page * PAGE_SIZE,
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MM_PG_RW | MM_PG_PRESENT | MM_PG_NOCACHE);
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}
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bool irqs_support = false;
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if (!pci_msi_init(pci_info.bus, pci_info.slot, pci_info.func, INTR_XHCI, thiscpu->lapic_id)) {
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uint8_t intr_line = pci_read8(pci_info.bus, pci_info.slot, pci_info.func, PCI_INTERRUPT_LINE);
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uint8_t intr_pin = pci_read8(pci_info.bus, pci_info.slot, pci_info.func, PCI_INTERRUPT_PIN);
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if (intr_pin != 0) {
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irqs_support = true;
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ioapic_route_irq(INTR_XHCI, intr_line, 0, thiscpu->lapic_id);
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}
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} else {
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irqs_support = true;
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}
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DEBUG("IRQ support=%d\n", irqs_support);
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if (!irqs_support) {
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return false;
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}
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struct xhci_init init = {
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.xhci_mmio_base = xhci_base,
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.irqs_support = irqs_support,
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.irq = INTR_XHCI,
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};
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device_op_func_t ops[] = {
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[XUSBCTRL_POLL_DRIVER] = &xhci_poll_driver,
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};
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device_create(DEVICE_TYPE_USB_CTRL, "xhci", ops, lengthof(ops), &xhci_init, &xhci_fini, &init,
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proc, rctx);
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xhci_init_done = true;
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return true;
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}
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