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XHCI big clean up, #define necessary bits for readability, change .clang-format options
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This commit is contained in:
Kamil Kowalczyk
2026-03-31 22:51:51 +02:00
parent 8f1e24653d
commit ee0e56928d
14 changed files with 401 additions and 119 deletions
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42
kernel/device/pci/pci.c
View File

@@ -21,8 +21,11 @@ static spin_lock_t pci_lock = SPIN_LOCK_INIT;
uint32_t pci_read32 (uint8_t bus, uint8_t slot, uint8_t func, uint8_t offset) {
uint64_t fpci;
uint32_t addr = (uint32_t)((uint32_t)bus << 16) | ((uint32_t)slot << 11) | ((uint32_t)func << 8) |
(offset & 0xFC) | ((uint32_t)0x80000000);
uint32_t addr = (uint32_t)((uint32_t)bus << 16) |
((uint32_t)slot << 11) |
((uint32_t)func << 8) |
(offset & 0xFC) |
((uint32_t)0x80000000);
spin_lock (&pci_lock, &fpci);
@@ -37,8 +40,11 @@ uint32_t pci_read32 (uint8_t bus, uint8_t slot, uint8_t func, uint8_t offset) {
void pci_write32 (uint8_t bus, uint8_t slot, uint8_t func, uint8_t offset, uint32_t value) {
uint64_t fpci;
uint32_t addr = (uint32_t)((uint32_t)bus << 16) | ((uint32_t)slot << 11) | ((uint32_t)func << 8) |
(offset & 0xFC) | ((uint32_t)0x80000000);
uint32_t addr = (uint32_t)((uint32_t)bus << 16) |
((uint32_t)slot << 11) |
((uint32_t)func << 8) |
(offset & 0xFC) |
((uint32_t)0x80000000);
spin_lock (&pci_lock, &fpci);
@@ -51,8 +57,11 @@ void pci_write32 (uint8_t bus, uint8_t slot, uint8_t func, uint8_t offset, uint3
uint16_t pci_read16 (uint8_t bus, uint8_t slot, uint8_t func, uint8_t offset) {
uint64_t fpci;
uint32_t addr = (uint32_t)((uint32_t)bus << 16) | ((uint32_t)slot << 11) | ((uint32_t)func << 8) |
(offset & 0xFC) | ((uint32_t)0x80000000);
uint32_t addr = (uint32_t)((uint32_t)bus << 16) |
((uint32_t)slot << 11) |
((uint32_t)func << 8) |
(offset & 0xFC) |
((uint32_t)0x80000000);
spin_lock (&pci_lock, &fpci);
@@ -67,8 +76,11 @@ uint16_t pci_read16 (uint8_t bus, uint8_t slot, uint8_t func, uint8_t offset) {
void pci_write16 (uint8_t bus, uint8_t slot, uint8_t func, uint8_t offset, uint16_t value) {
uint64_t fpci;
uint32_t addr = (uint32_t)((uint32_t)bus << 16) | ((uint32_t)slot << 11) | ((uint32_t)func << 8) |
(offset & 0xFC) | ((uint32_t)0x80000000);
uint32_t addr = (uint32_t)((uint32_t)bus << 16) |
((uint32_t)slot << 11) |
((uint32_t)func << 8) |
(offset & 0xFC) |
((uint32_t)0x80000000);
spin_lock (&pci_lock, &fpci);
@@ -81,8 +93,11 @@ void pci_write16 (uint8_t bus, uint8_t slot, uint8_t func, uint8_t offset, uint1
uint8_t pci_read8 (uint8_t bus, uint8_t slot, uint8_t func, uint8_t offset) {
uint64_t fpci;
uint32_t addr = (uint32_t)((uint32_t)bus << 16) | ((uint32_t)slot << 11) | ((uint32_t)func << 8) |
(offset & 0xFC) | ((uint32_t)0x80000000);
uint32_t addr = (uint32_t)((uint32_t)bus << 16) |
((uint32_t)slot << 11) |
((uint32_t)func << 8) |
(offset & 0xFC) |
((uint32_t)0x80000000);
spin_lock (&pci_lock, &fpci);
@@ -97,8 +112,11 @@ uint8_t pci_read8 (uint8_t bus, uint8_t slot, uint8_t func, uint8_t offset) {
void pci_write8 (uint8_t bus, uint8_t slot, uint8_t func, uint8_t offset, uint8_t value) {
uint64_t fpci;
uint32_t addr = (uint32_t)((uint32_t)bus << 16) | ((uint32_t)slot << 11) | ((uint32_t)func << 8) |
(offset & 0xFC) | ((uint32_t)0x80000000);
uint32_t addr = (uint32_t)((uint32_t)bus << 16) |
((uint32_t)slot << 11) |
((uint32_t)func << 8) |
(offset & 0xFC) |
((uint32_t)0x80000000);
spin_lock (&pci_lock, &fpci);

7
kernel/device/storage/idedrv.c
View File

@@ -177,9 +177,10 @@ void ide_probe (uint16_t io, uint16_t ctrl, uint8_t devno, struct ide_probe* pro
probe->flags |= IDE_PROBE_LBA48;
if ((probe->flags & IDE_PROBE_LBA48)) {
probe->sector_count =
(size_t)((uint64_t)identify_buffer[100] | ((uint64_t)identify_buffer[101] << 16) |
((uint64_t)identify_buffer[102] << 32) | ((uint64_t)identify_buffer[103] << 48));
probe->sector_count = (size_t)((uint64_t)identify_buffer[100] |
((uint64_t)identify_buffer[101] << 16) |
((uint64_t)identify_buffer[102] << 32) |
((uint64_t)identify_buffer[103] << 48));
} else {
probe->sector_count =
(size_t)((uint64_t)identify_buffer[60] | ((uint64_t)identify_buffer[61] << 16));

304
kernel/device/usb/xhci.c
View File

@@ -58,6 +58,56 @@
#define XHCI_ERSTBA 0x10
#define XHCI_ERDP 0x18
/* HCCPARAMS1 */
#define XHCI_HCCPARAMS1_AC64 0
#define XHCI_HCCPARAMS1_BNC 1
#define XHCI_HCCPARAMS1_CSZ 2
#define XHCI_HCCPARAMS1_PPC 3
#define XHCI_HCCPARAMS1_PIND 4
#define XHCI_HCCPARAMS1_LHRC 5
#define XHCI_HCCPARAMS1_LTC 6
#define XHCI_HCCPARAMS1_NSS 7
#define XHCI_HCCPARAMS1_PAE 8
#define XHCI_HCCPARAMS1_SPC 9
#define XHCI_HCCPARAMS1_SEC 10
#define XHCI_HCCPARAMS1_CFC 11
#define XHCI_HCCPARAMS1_MAX_PSA_SIZE 12
#define XHCI_HCCPARAMS1_XECP 16
/* XHCI extended capabilities */
#define XHCI_XECP_CAP_ID 0
#define XHCI_XECP_NEXT_PTR 8
/* USB legacy support capability */
#define XHCI_USBLEGSUP_CAP_ID 0
#define XHCI_USBLEGSUP_NEXT_PTR 8
#define XHCI_USBLEGSUP_BIOS_SEMA 16
#define XHCI_USBLEGSUP_OS_SEMA 24
/* Supported protocol capability */
#define XHCI_SUPPROTO_DW0_CAP_ID 0
#define XHCI_SUPPROTO_DW0_NEXT_PTR 8
#define XHCI_SUPPROTO_DW0_MINOR_REV 16
#define XHCI_SUPPROTO_DW0_MAJOR_REV 24
#define XHCI_SUPPROTO_DW1_NAME_STRING 0
#define XHCI_SUPPROTO_DW2_PORT_OFF 0
#define XHCI_SUPPROTO_DW2_PORT_COUNT 8
#define XHCI_SUPPROTO_DW2_PROT_DEF 16
#define XHCI_SUPPROTO_DW2_PSIC 28
#define XHCI_SUPPROTO_DW3_SLOT_TYPE 0
/* HCSPARAMS1 */
#define XHCI_HCSPARAMS1_MAX_DEV_SLOTS 0
#define XHCI_HCSPARAMS1_MAX_INTRS 8
#define XHCI_HCSPARAMS1_MAX_PORTS 24
/* HCSPARAMS2 */
#define XHCI_HCSPARAMS2_IST 0
#define XHCI_HCSPARAMS2_ERST_MAX 4
#define XHCI_HCSPARAMS2_MAX_SCRTCH_HI 21
#define XHCI_HCSPARAMS2_SPR 26
#define XHCI_HCSPARAMS2_MAX_SCRTCH_LO 27
/* event types */
#define XHCI_TRB_NORMAL 1
#define XHCI_TRB_SETUP_STAGE 2
@@ -93,6 +143,74 @@
#define XHCI_TRB_DEV_NOTIF_EVNT 38
#define XHCI_TRB_MFINDEX_WRAP 39
/* generic TRB bits */
#define XHCI_GTRB_TRB_TYPE 10
#define XHCI_GTRB_CYCLE_BIT 0
/* command completion event TRB */
#define XHCI_CCETRB_CTRL_SLOT_ID 24
#define XHCI_CCETRB_CTRL_VFID 16
#define XHCI_CCETRB_CTRL_TRB_TYPE 10
#define XHCI_CCETRB_CTRL_CYCLEBIT 0
#define XHCI_CCETRB_STS_CMPL_CODE 24
/* transfer event TRB */
#define XHCI_TETRB_CTRL_SLOT_ID 24
#define XHCI_TETRB_CTRL_ENDPOINT 16
#define XHCI_TETRB_CTRL_TRB_TYPE 10
#define XHCI_TETRB_CTRL_EVT_DATA 2
#define XHCI_TETRB_CTRL_CYCLEBIT 0
#define XHCI_TETRB_STS_CMPL_CODE 24
/* port status change event TRB */
#define XHCI_PSCETRB_CTRL_TRB_TYPE 10
#define XHCI_PSCETRB_CTRL_CYCLEBIT 0
#define XHCI_PSCETRB_STS_CMPL_CODE 24
#define XHCI_PSCETRB_PARAM_PORT_ID 24
/* link TRB */
#define XHCI_LNKTRB_CTRL_TRB_TYPE 10
#define XHCI_LNKTRB_CTRL_IOC 5
#define XHCI_LNKTRB_CTRL_CH 4
#define XHCI_LNKTRB_CTRL_TC 1
#define XHCI_LNKTRB_CTRL_CYCLEBIT 0
#define XHCI_LNKTRB_STS_INTR_TRGT 22
/* setup stage TRB */
#define XHCI_SSTRB_CTRL_TRT 16
#define XHCI_SSTRB_CTRL_TRB_TYPE 10
#define XHCI_SSTRB_CTRL_IDT 6
#define XHCI_SSTRB_CTRL_IOC 5
#define XHCI_SSTRB_CTRL_CYCLEBIT 0
#define XHCI_SSTRB_STS_INTR_TRGT 22
#define XHCI_SSTRB_PARAM_WLENGTH 48
#define XHCI_SSTRB_PARAM_WINDEX 32
#define XHCI_SSTRB_PARAM_WVALUE 16
#define XHCI_SSTRB_PARAM_BREQUEST 8
#define XHCI_SSTRB_PARAM_BMREQUEST_TYPE 0
/* data stage TRB */
#define XHCI_DSTRB_CTRL_DIR 16
#define XHCI_DSTRB_CTRL_TRB_TYPE 10
#define XHCI_DSTRB_CTRL_IDT 6
#define XHCI_DSTRB_CTRL_IOC 5
#define XHCI_DSTRB_CTRL_CH 4
#define XHCI_DSTRB_CTRL_NS 3
#define XHCI_DSTRB_CTRL_ISP 2
#define XHCI_DSTRB_CTRL_ENT 1
#define XHCI_DSTRB_CTRL_CYCLEBIT 0
#define XHCI_DSTRB_STS_INTR_TRGT 22
#define XHCI_DSTRB_STS_TD_SIZE 17
/* status stage TRB */
#define XHCI_STSTRB_CTRL_DIR 16
#define XHCI_STSTRB_CTRL_TRB_TYPE 10
#define XHCI_STSTRB_CTRL_IOC 5
#define XHCI_STSTRB_CTRL_CH 4
#define XHCI_STSTRB_CTRL_ENT 1
#define XHCI_STSTRB_CTRL_CYCLEBIT 0
#define XHCI_STSTRB_STS_INTR_TRGT 22
/* extended capabilities */
#define XHCI_EXTCAP_USB_LEGACY_SUPPORT 1
#define XHCI_EXTCAP_SUPPORTED_PROTOCOL 2
@@ -104,6 +222,73 @@
#define XHCI_EXTCAP_EXT_MSG_INTR 8
#define XHCI_EXTCAP_VENDOR_DEFINED 9
/* PORTSC bits */
#define XHCI_PORTSC_CCS 0
#define XHCI_PORTSC_PED 1
#define XHCI_PORTSC_OCA 3
#define XHCI_PORTSC_PR 4
#define XHCI_PORTSC_PLS 5
#define XHCI_PORTSC_PP 9
#define XHCI_PORTSC_PORTSPEED 10
#define XHCI_PORTSC_PIC 14
#define XHCI_PORTSC_LWS 16
#define XHCI_PORTSC_CSC 17
#define XHCI_PORTSC_PEC 18
#define XHCI_PORTSC_WRC 19
#define XHCI_PORTSC_OCC 20
#define XHCI_PORTSC_PRC 21
#define XHCI_PORTSC_PLC 22
#define XHCI_PORTSC_CEC 23
#define XHCI_PORTSC_CAS 24
#define XHCI_PORTSC_WCE 25
#define XCHI_PORTSC_WDE 26
#define XHCI_PORTSC_WOE 27
#define XHCI_PORTSC_DR 30
#define XHCI_PORTSC_WPR 31
/* endpoint context */
#define XHCI_EPCTX_EP_STATE 0
#define XHCI_EPCTX_MULT 8
#define XHCI_EPCTX_MAXPSTRAMS 10
#define XHCI_EPCTX_LSA 15
#define XHCI_EPCTX_INTERVAL 16
#define XHCI_EPCTX_MAX_ESIT_HI 24
#define XHCI_EPCTX_ERR_COUNT 1
#define XHCI_EPCTX_EP_TYPE 3
#define XHCI_EPCTX_HID 7
#define XHCI_EPCTX_MAX_BURST_SZ 8
#define XHCI_EPCTX_MAX_PKT_SZ 16
#define XHCI_EPCTX_DCS 0
#define XHCI_EPCTX_TR_DQ_PTR 4
#define XHCI_EPCTX_AVG_TRB_LEN 0
#define XHCI_EPCTX_MAX_ESIT_LOW 16
/* endpoint types */
#define XHCI_EP_INVALID 0
#define XHCI_EP_ISOCH_OUT 1
#define XHCI_EP_BULK_OUT 2
#define XHCI_EP_INTR_OUT 3
#define XHCI_EP_CTRL_BI 4
#define XHCI_EP_ISOCH_IN 5
#define XHCI_EP_BULK_IN 6
#define XHCI_EP_INTR_IN 7
/* slot context */
#define XHIC_SLCTX_ROUTE_STR 0
#define XHCI_SLCTX_SPEED 20
#define XHCI_SLCTX_MTT 25
#define XHCI_SLCTX_HUB 26
#define XHCI_SLCTX_CTX_ENTRIES 27
#define XHCI_SLCTX_MAXEXITLTNCY 0
#define XHCI_SLCTX_ROOTHUBPRNUM 16
#define XHCI_SLCTX_PORT_COUNT 24
#define XHCI_SLCTX_PRNT_HUB_SLT 0
#define XHCI_SLCTX_PARENT_PORT 8
#define XHCI_SLCTX_TT_THINKTIME 16
#define XHCI_SLCTX_INTR_TARGET 22
#define XHCI_SLCTX_USB_DEV_ADDR 0
#define XHCI_SLCTX_SLOT_STATE 27
/* clang-format on */
static void xhci_write8 (uintptr_t base, uint32_t reg, uint8_t value) {
@@ -146,8 +331,8 @@ static void xhci_port_reset (struct xhci* xhci, uint8_t port) {
uint32_t portsc = xhci_portsc_read (xhci, port);
/* check Port Power */
if (!(portsc & (1 << 9))) {
portsc |= (1 << 9);
if (!(portsc & (1 << XHCI_PORTSC_PP))) {
portsc |= (1 << XHCI_PORTSC_PP);
xhci_portsc_write (xhci, port, portsc);
stall_ms (50);
@@ -155,27 +340,25 @@ static void xhci_port_reset (struct xhci* xhci, uint8_t port) {
portsc = xhci_portsc_read (xhci, port);
}
/* connect status change, enable port, port reset change */
portsc |= (1 << 17) | (1 << 18) | (1 << 21);
portsc |= (1 << XHCI_PORTSC_CSC) | (1 << XHCI_PORTSC_PEC) | (1 << XHCI_PORTSC_PRC);
xhci_portsc_write (xhci, port, portsc);
if (xhci_port->type == XHCI_PORT_USB3) {
/* warm port reset */
portsc |= (1 << 31);
portsc |= (1 << XHCI_PORTSC_WPR);
} else if (xhci_port->type == XHCI_PORT_USB2) {
/* port reset */
portsc |= (1 << 4);
portsc |= (1 << XHCI_PORTSC_PR);
}
xhci_portsc_write (xhci, port, portsc);
stall_ms (500);
/* warm port reset change, port reset change , connect status change, port enabled change */
portsc |= (1 << 21) | (1 << 19) | (1 << 17) | (1 << 18);
/* port enabled */
portsc &= ~(1 << 1);
portsc |= (1 << XHCI_PORTSC_PRC) |
(1 << XHCI_PORTSC_WRC) |
(1 << XHCI_PORTSC_CSC) |
(1 << XHCI_PORTSC_PEC);
portsc &= ~(1 << XHCI_PORTSC_PED);
xhci_portsc_write (xhci, port, portsc);
@@ -217,8 +400,8 @@ static void xhci_delete_pdevice (struct xhci* xhci, uint8_t port) {
static void xhci_event_dispatch (struct xhci* xhci, struct xhci_trb* event, uint8_t type) {
switch (type) {
case XHCI_TRB_CMD_CMPL_EVENT: {
uint8_t cmpl_code = (event->status >> 24) & 0xFF;
uint8_t slot_id = (event->ctrl >> 24) & 0xFF;
uint8_t cmpl_code = (event->status >> XHCI_CCETRB_STS_CMPL_CODE) & 0xFF;
uint8_t slot_id = (event->ctrl >> XHCI_CCETRB_CTRL_SLOT_ID) & 0xFF;
DEBUG ("cmd completion: code=%u,slot=%u\n", cmpl_code, slot_id);
@@ -226,13 +409,13 @@ static void xhci_event_dispatch (struct xhci* xhci, struct xhci_trb* event, uint
xhci->last_cmpl_code = cmpl_code;
} break;
case XHCI_TRB_PORT_STS_CHNG: {
uint8_t port = ((event->param >> 24) & 0xFF) - 1;
uint8_t port = ((event->param >> XHCI_PSCETRB_PARAM_PORT_ID) & 0xFF) - 1;
uint32_t portsc = xhci_portsc_read (xhci, port);
DEBUG ("Status change on port %u: 0x%08x\n", port, portsc);
/* ack. PED + PR */
portsc &= ~((1 << 1) | (1 << 4));
portsc &= ~((1 << XHCI_PORTSC_PED) | (1 << XHCI_PORTSC_PR));
xhci_portsc_write (xhci, port, portsc);
@@ -242,9 +425,9 @@ static void xhci_event_dispatch (struct xhci* xhci, struct xhci_trb* event, uint
list_append (xhci->port_changes, &change->port_changes_link);
} break;
case XHCI_TRB_TRANSFER_EVENT: {
uint8_t cmpl_code = (event->status >> 24) & 0xFF;
uint8_t slot_id = (event->ctrl >> 24) & 0xFF;
uint8_t endpoint_id = (event->ctrl >> 16) & 0x1F;
uint8_t cmpl_code = (event->status >> XHCI_TETRB_STS_CMPL_CODE) & 0xFF;
uint8_t slot_id = (event->ctrl >> XHCI_TETRB_CTRL_SLOT_ID) & 0xFF;
uint8_t endpoint_id = (event->ctrl >> XHCI_TETRB_CTRL_ENDPOINT) & 0x1F;
DEBUG ("transfer completion: code=%u,slot=%u,endpoint_id=%u\n", cmpl_code, slot_id,
endpoint_id);
@@ -263,13 +446,13 @@ static void xhci_poll_events (struct xhci* xhci) {
for (;;) {
struct xhci_trb* event = &xhci->event_ring[xhci->event_ring_idx];
if ((event->ctrl & 0x1) != xhci->event_cycle_bit) {
if ((event->ctrl & (1 << XHCI_GTRB_CYCLE_BIT)) != xhci->event_cycle_bit) {
break;
}
serviced = true;
uint8_t type = (event->ctrl >> 10) & 0x3F;
uint8_t type = (event->ctrl >> XHCI_GTRB_TRB_TYPE) & 0x3F;
xhci_event_dispatch (xhci, event, type);
@@ -317,7 +500,9 @@ static void xhci_endpoint0_put_trb (struct xhci_pdevice* pdevice, struct xhci_tr
struct xhci_trb* link = &pdevice->endpoint0_ring[pdevice->endpoint0_ring_idx];
link->param = pdevice->endpoint0_ring_phys;
link->status = 0;
link->ctrl = (XHCI_TRB_LINK << 10) | (1 << 1) | pdevice->endpoint0_cycle_bit;
link->ctrl = (XHCI_TRB_LINK << XHCI_LNKTRB_CTRL_TRB_TYPE) |
(1 << XHCI_LNKTRB_CTRL_TC) |
pdevice->endpoint0_cycle_bit;
pdevice->endpoint0_ring_idx = 0;
pdevice->endpoint0_cycle_bit ^= 1;
@@ -335,8 +520,13 @@ static bool xhci_endpoint0_ctrl_in (struct xhci* xhci, struct xhci_pdevice* pdev
uint8_t request_type, uint8_t request, uint16_t value,
uint16_t index, uintptr_t data_phys, uint16_t length,
uint64_t* lockflags) {
uint64_t setup = ((uint64_t)length << 48) | ((uint64_t)index << 32) | ((uint64_t)value << 16) |
((uint64_t)request << 8) | ((uint64_t)request_type);
/* clang-format off */
uint64_t setup = ((uint64_t)length << XHCI_SSTRB_PARAM_WLENGTH)
| ((uint64_t)index << XHCI_SSTRB_PARAM_WINDEX)
| ((uint64_t)value << XHCI_SSTRB_PARAM_WVALUE)
| ((uint64_t)request << XHCI_SSTRB_PARAM_BREQUEST)
| ((uint64_t)request_type << XHCI_SSTRB_PARAM_BMREQUEST_TYPE);
/* clang-format on */
struct xhci_trb trb;
@@ -347,21 +537,23 @@ static bool xhci_endpoint0_ctrl_in (struct xhci* xhci, struct xhci_pdevice* pdev
memset (&trb, 0, sizeof (trb));
trb.param = setup;
trb.status = 8;
trb.ctrl = (XHCI_TRB_SETUP_STAGE << 10) | (1 << 6) | (1 << 4);
trb.ctrl =
(XHCI_TRB_SETUP_STAGE << XHCI_SSTRB_CTRL_TRB_TYPE) | (1 << XHCI_SSTRB_CTRL_IDT) | (1 << 4);
xhci_endpoint0_put_trb (pdevice, trb);
/* data stage */
memset (&trb, 0, sizeof (trb));
trb.param = data_phys;
trb.status = length;
trb.ctrl = (XHCI_TRB_DATA_STAGE << 10) | (1 << 16) | (1 << 4);
trb.ctrl =
(XHCI_TRB_DATA_STAGE << XHCI_DSTRB_CTRL_TRB_TYPE) | (1 << XHCI_DSTRB_CTRL_DIR) | (1 << 4);
xhci_endpoint0_put_trb (pdevice, trb);
/* status stage */
memset (&trb, 0, sizeof (trb));
trb.param = 0;
trb.status = 0;
trb.ctrl = (XHCI_TRB_STATUS_STAGE << 10) | (1 << 5);
trb.ctrl = (XHCI_TRB_STATUS_STAGE << XHCI_STSTRB_CTRL_TRB_TYPE) | (1 << XHCI_STSTRB_CTRL_IOC);
xhci_endpoint0_put_trb (pdevice, trb);
xhci_write32 (xhci->xhci_doorbell_base, pdevice->slot_id * 4, 1);
@@ -390,7 +582,9 @@ static void xhci_send_cmd (struct xhci* xhci, uint64_t param, uint32_t status, u
struct xhci_trb* link = &xhci->cmd_ring[xhci->cmd_ring_idx];
link->param = xhci->cmd_ring_phys;
link->status = 0;
link->ctrl = (XHCI_TRB_LINK << 10) | (1 << 1) | xhci->cmd_cycle_bit;
link->ctrl = (XHCI_TRB_LINK << XHCI_LNKTRB_CTRL_TRB_TYPE) |
(1 << XHCI_LNKTRB_CTRL_TC) |
xhci->cmd_cycle_bit;
xhci->cmd_ring_idx = 0;
xhci->cmd_cycle_bit ^= 1;
@@ -399,7 +593,7 @@ static void xhci_send_cmd (struct xhci* xhci, uint64_t param, uint32_t status, u
struct xhci_trb* trb = &xhci->cmd_ring[xhci->cmd_ring_idx];
trb->param = param;
trb->status = status;
trb->ctrl = (ctrl & ~0x1) | xhci->cmd_cycle_bit;
trb->ctrl = (ctrl & ~XHCI_LNKTRB_CTRL_TC) | xhci->cmd_cycle_bit;
xhci->cmd_ring_idx++;
@@ -428,7 +622,7 @@ static void xhci_send_cmd (struct xhci* xhci, uint64_t param, uint32_t status, u
static void xhci_bios_handover (struct xhci* xhci) {
uint32_t hccparams1 = xhci_read32 (xhci->xhci_mmio_base, XHCI_HCCPARAMS1);
uint32_t ext_offset = (hccparams1 >> 16) << 2;
uint32_t ext_offset = (hccparams1 >> XHCI_HCCPARAMS1_XECP) << 2;
if (ext_offset == 0)
return;
@@ -440,7 +634,7 @@ static void xhci_bios_handover (struct xhci* xhci) {
if (cap_id == XHCI_EXTCAP_USB_LEGACY_SUPPORT) {
/* Make or break on real hardware. We need to take over ownership from the BIOS. */
if (cap & (1 << 16)) {
if (cap & (1 << XHCI_USBLEGSUP_BIOS_SEMA)) {
DEBUG ("BIOS owns XHCI, requesting handover!\n");
xhci_write8 (cap_ptr, 3, 1);
@@ -449,7 +643,7 @@ static void xhci_bios_handover (struct xhci* xhci) {
int timeout = 1000;
while (--timeout > 0) {
uint32_t val = xhci_read32 (cap_ptr, 0);
if (!(val & (1 << 16)) && (val & (1 << 24)))
if (!(val & (1 << XHCI_USBLEGSUP_BIOS_SEMA)) && (val & (1 << XHCI_USBLEGSUP_OS_SEMA)))
break;
stall_ms (100);
@@ -461,7 +655,7 @@ static void xhci_bios_handover (struct xhci* xhci) {
break;
}
uint8_t next = (cap >> 8) & 0xFF;
uint8_t next = (cap >> XHCI_XECP_NEXT_PTR) & 0xFF;
if (!next)
break;
@@ -471,7 +665,7 @@ static void xhci_bios_handover (struct xhci* xhci) {
static void xhci_reset_ports (struct xhci* xhci) {
uint32_t hccparams1 = xhci_read32 (xhci->xhci_mmio_base, XHCI_HCCPARAMS1);
uint32_t ext_offset = (hccparams1 >> 16) << 2;
uint32_t ext_offset = (hccparams1 >> XHCI_HCCPARAMS1_XECP) << 2;
if (ext_offset == 0)
return;
@@ -480,13 +674,14 @@ static void xhci_reset_ports (struct xhci* xhci) {
uintptr_t cap_ptr = xhci->xhci_mmio_base + ext_offset;
uint32_t cap = xhci_read32 (cap_ptr, 0);
uint8_t cap_id = cap & 0xFF;
uint8_t minor = (cap >> 16) & 0xFF;
uint8_t major = (cap >> 24) & 0xFF;
if (cap_id == XHCI_EXTCAP_SUPPORTED_PROTOCOL) {
uint8_t minor = (cap >> XHCI_SUPPROTO_DW0_MINOR_REV) & 0xFF;
uint8_t major = (cap >> XHCI_SUPPROTO_DW0_MAJOR_REV) & 0xFF;
uint32_t dword2 = xhci_read32 (cap_ptr, 8);
uint8_t port_off = dword2 & 0xFF;
uint8_t port_count = (dword2 >> 8) & 0xFF;
uint8_t port_off = (dword2 >> XHCI_SUPPROTO_DW2_PORT_OFF) & 0xFF;
uint8_t port_count = (dword2 >> XHCI_SUPPROTO_DW2_PORT_COUNT) & 0xFF;
uint8_t first_port = port_off - 1;
uint8_t last_port = first_port + port_count - 1;
@@ -506,7 +701,7 @@ static void xhci_reset_ports (struct xhci* xhci) {
uint32_t portsc = xhci_portsc_read (xhci, port);
if ((portsc & (1 << 0))) {
if ((portsc & (1 << XHCI_PORTSC_CCS))) {
DEBUG ("Device connected. resetting\n");
xhci_port_reset (xhci, port);
xhci_create_pdevice (xhci, port);
@@ -516,7 +711,7 @@ static void xhci_reset_ports (struct xhci* xhci) {
}
}
uint8_t next = (cap >> 8) & 0xFF;
uint8_t next = (cap >> XHCI_XECP_NEXT_PTR) & 0xFF;
if (!next)
break;
@@ -534,10 +729,10 @@ static void xhci_pdevice_setup_addressing (struct xhci* xhci, struct xhci_pdevic
uint32_t portsc = xhci_portsc_read (xhci, pdevice->port_value);
uint32_t speed = (portsc >> 10) & 0x0F;
uint32_t speed = (portsc >> XHCI_PORTSC_PORTSPEED) & 0x0F;
xhci->last_cmpl_code = 0;
xhci_send_cmd (xhci, 0, 0, XHCI_TRB_SLOT_ENAB_CMD << 10, lockflags);
xhci_send_cmd (xhci, 0, 0, XHCI_TRB_SLOT_ENAB_CMD << XHCI_GTRB_TRB_TYPE, lockflags);
if (xhci->last_cmpl_code != 1) {
DEBUG ("Enable slot failed\n");
@@ -571,11 +766,12 @@ static void xhci_pdevice_setup_addressing (struct xhci* xhci, struct xhci_pdevic
/* Add slot and endpoint 0 */
ctx64->ctrl.dw[1] = (1 << 0) | (1 << 1);
ctx64->slot.dw[0] = (1 << 27) | (speed << 20);
ctx64->slot.dw[1] = ((pdevice->port_value + 1) << 16);
ctx64->slot.dw[0] = (1 << XHCI_SLCTX_SLOT_STATE) | (speed << XHCI_SLCTX_SPEED);
ctx64->slot.dw[1] = ((pdevice->port_value + 1) << XHCI_SLCTX_ROOTHUBPRNUM);
ctx64->endpoints[0].dw[0] = 0;
ctx64->endpoints[0].dw[1] = 3 | (4 << 3) | (max_packet_size << 16);
ctx64->endpoints[0].dw[1] =
3 | (XHCI_EP_CTRL_BI << XHCI_EPCTX_EP_TYPE) | (max_packet_size << XHCI_EPCTX_MAX_PKT_SZ);
ctx64->endpoints[0].dw[2] = (uint32_t)pdevice->endpoint0_ring_phys | (1 << 0);
ctx64->endpoints[0].dw[3] = (uint32_t)(pdevice->endpoint0_ring_phys >> 32);
} else {
@@ -585,16 +781,17 @@ static void xhci_pdevice_setup_addressing (struct xhci* xhci, struct xhci_pdevic
ctx32->ctrl.dw[1] = (1 << 0) | (1 << 1);
ctx32->slot.dw[0] = (1 << 27) | (speed << 20);
ctx32->slot.dw[1] = ((pdevice->port_value + 1) << 16);
ctx32->slot.dw[0] = (1 << XHCI_SLCTX_SLOT_STATE) | (speed << XHCI_SLCTX_SPEED);
ctx32->slot.dw[1] = ((pdevice->port_value + 1) << XHCI_SLCTX_ROOTHUBPRNUM);
ctx32->endpoints[0].dw[1] = 3 | (4 << 3) | (max_packet_size << 16);
ctx32->endpoints[0].dw[1] =
3 | (XHCI_EP_CTRL_BI << XHCI_EPCTX_EP_TYPE) | (max_packet_size << XHCI_EPCTX_MAX_PKT_SZ);
ctx32->endpoints[0].dw[2] = (uint32_t)pdevice->endpoint0_ring_phys | (1 << 0);
ctx32->endpoints[0].dw[3] = (uint32_t)(pdevice->endpoint0_ring_phys >> 32);
}
xhci->last_cmpl_code = 0;
uint32_t ctrl = (pdevice->slot_id << 24) | (XHCI_TRB_ADDR_DEV_CMD << 10);
uint32_t ctrl = (pdevice->slot_id << 24) | (XHCI_TRB_ADDR_DEV_CMD << XHCI_GTRB_TRB_TYPE);
xhci_send_cmd (xhci, input_ctx_phys, 0, ctrl, lockflags);
stall_ms (500);
@@ -661,8 +858,8 @@ static void xhci_poll_port_changes (struct xhci* xhci) {
list_remove (xhci->port_changes, &change->port_changes_link);
if ((change->portsc & (1 << 17))) {
if ((change->portsc & (1 << 0))) {
if ((change->portsc & (1 << XHCI_PORTSC_CSC))) {
if ((change->portsc & (1 << XHCI_PORTSC_CCS))) {
DEBUG ("Device attached to port %u!\n", change->port);
xhci_port_reset (xhci, change->port);
@@ -718,10 +915,11 @@ DEFINE_DEVICE_INIT (xhci_init) {
xhci->xhci_doorbell_base = xhci->xhci_mmio_base + dboff;
uint32_t hcsparams2 = xhci_read32 (xhci->xhci_mmio_base, XHCI_HCSPARAMS2);
xhci->max_scratchpad = (((hcsparams2 >> 21) & 0x1F) << 5) | ((hcsparams2 >> 27) & 0x1F);
xhci->max_scratchpad = (((hcsparams2 >> XHCI_HCSPARAMS2_MAX_SCRTCH_HI) & 0x1F) << 5) |
((hcsparams2 >> XHCI_HCSPARAMS2_MAX_SCRTCH_LO) & 0x1F);
uint32_t hccparams1 = xhci_read32 (xhci->xhci_mmio_base, XHCI_HCCPARAMS1);
xhci->xhci_ctx_size = (hccparams1 & (1 << 2)) ? 64 : 32;
xhci->xhci_ctx_size = (hccparams1 & (1 << XHCI_HCCPARAMS1_CSZ)) ? 64 : 32;
DEBUG ("starting init sequence\n");