Introduce concept of Process Resources (PR_MEM), implement necessary syscalls

kernel/amd64/mm.c

@@ -251,6 +251,148 @@ void mm_reload (void) {
   spin_unlock (&mm_lock);
 }
 
+bool mm_validate (struct pd* pd, uintptr_t vaddr, uint32_t flags) {
+  spin_lock (&mm_lock);
+
+  struct limine_hhdm_response* hhdm = limine_hhdm_request.response;
+  bool ret = false;
+
+  if (flags & MM_PD_LOCK)
+    spin_lock (&pd->lock);
+
+  uint64_t* pml4 = (uint64_t*)(pd->cr3_paddr + (uintptr_t)hhdm->offset);
+  struct pg_index pg_index = amd64_mm_page_index (vaddr);
+
+  uint64_t* pml3 = amd64_mm_next_table (pml4, pg_index.pml4, false);
+  if (pml3 == NULL)
+    goto done;
+
+  uint64_t* pml2 = amd64_mm_next_table (pml3, pg_index.pml3, false);
+  if (pml2 == NULL)
+    goto done;
+
+  uint64_t* pml1 = amd64_mm_next_table (pml2, pg_index.pml2, false);
+  if (pml1 == NULL)
+    goto done;
+
+  uint64_t pte = pml1[pg_index.pml1];
+  ret = (pte & AMD64_PG_PRESENT) != 0;
+
+done:
+  if (flags & MM_PD_LOCK)
+    spin_unlock (&pd->lock);
+
+  spin_unlock (&mm_lock);
+
+  return ret;
+}
+
+bool mm_validate_buffer (struct pd* pd, uintptr_t vaddr, size_t size, uint32_t flags) {
+  bool ok = true;
+
+  if (flags & MM_PD_LOCK)
+    spin_lock (&pd->lock);
+
+  for (size_t i = 0; i < size; i++) {
+    ok = mm_validate (pd, vaddr + i, 0);
+    if (!ok)
+      goto done;
+  }
+
+done:
+  if (flags & MM_PD_LOCK)
+    spin_unlock (&pd->lock);
+
+  return ok;
+}
+
+uintptr_t mm_p2v (struct pd* pd, uintptr_t paddr, uint32_t flags) {
+  spin_lock (&mm_lock);
+
+  struct limine_hhdm_response* hhdm = limine_hhdm_request.response;
+  uintptr_t ret = 0;
+
+  if (flags & MM_PD_LOCK)
+    spin_lock (&pd->lock);
+
+  uint64_t* pml4 = (uint64_t*)(pd->cr3_paddr + (uintptr_t)hhdm->offset);
+
+  for (size_t i4 = 0; i4 < 512; i4++) {
+    if (!(pml4[i4] & AMD64_PG_PRESENT))
+      continue;
+
+    uint64_t* pml3 = (uint64_t*)((uintptr_t)hhdm->offset + (pml4[i4] & ~0xFFFULL));
+    for (size_t i3 = 0; i3 < 512; i3++) {
+      if (!(pml3[i3] & AMD64_PG_PRESENT))
+        continue;
+
+      uint64_t* pml2 = (uint64_t*)((uintptr_t)hhdm->offset + (pml3[i3] & ~0xFFFULL));
+      for (size_t i2 = 0; i2 < 512; i2++) {
+        if (!(pml2[i2] & AMD64_PG_PRESENT))
+          continue;
+
+        uint64_t* pml1 = (uint64_t*)((uintptr_t)hhdm->offset + (pml2[i2] & ~0xFFFULL));
+        for (size_t i1 = 0; i1 < 512; i1++) {
+          if ((pml1[i1] & AMD64_PG_PRESENT) && ((pml1[i1] & ~0xFFFULL) == (paddr & ~0xFFFULL))) {
+            struct pg_index idx = {i4, i3, i2, i1};
+            ret = (((uint64_t)idx.pml4 << 39) | ((uint64_t)idx.pml3 << 30) |
+                   ((uint64_t)idx.pml2 << 21) | ((uint64_t)idx.pml1 << 12) | (paddr & 0xFFFULL));
+            goto done;
+          }
+        }
+      }
+    }
+  }
+
+done:
+  if (flags & MM_PD_LOCK)
+    spin_unlock (&pd->lock);
+
+  spin_unlock (&mm_lock);
+
+  return ret;
+}
+
+uintptr_t mm_v2p (struct pd* pd, uintptr_t vaddr, uint32_t flags) {
+  spin_lock (&mm_lock);
+
+  struct limine_hhdm_response* hhdm = limine_hhdm_request.response;
+  uintptr_t ret = 0;
+
+  if (flags & MM_PD_LOCK)
+    spin_lock (&pd->lock);
+
+  uint64_t* pml4 = (uint64_t*)(pd->cr3_paddr + (uintptr_t)hhdm->offset);
+  struct pg_index pg_index = amd64_mm_page_index (vaddr);
+
+  uint64_t* pml3 = amd64_mm_next_table (pml4, pg_index.pml4, false);
+  if (pml3 == NULL)
+    goto done;
+
+  uint64_t* pml2 = amd64_mm_next_table (pml3, pg_index.pml3, false);
+  if (pml2 == NULL)
+    goto done;
+
+  uint64_t* pml1 = amd64_mm_next_table (pml2, pg_index.pml2, false);
+  if (pml1 == NULL)
+    goto done;
+
+  uint64_t pte = pml1[pg_index.pml1];
+
+  if (!(pte & AMD64_PG_PRESENT))
+    goto done;
+
+  ret = ((pte & ~0xFFFULL) | (vaddr & 0xFFFULL));
+
+done:
+  if (flags & MM_PD_LOCK)
+    spin_unlock (&pd->lock);
+
+  spin_unlock (&mm_lock);
+
+  return ret;
+}
+
 /* TLB shootdown IRQ handler */
 static void amd64_tlb_shootdown_irq (void* arg, void* regs) {
   (void)arg, (void)regs;