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Remove amd64_ platform prefix

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This commit is contained in:
Kamil Kowalczyk
2026-02-20 15:33:16 +01:00
parent 4472ad5bb3
commit c68b00f2ea
28 changed files with 236 additions and 246 deletions
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74
kernel/amd64/apic.c
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@@ -56,7 +56,7 @@ static size_t intr_src_override_entries = 0;
static spin_lock_t lapic_calibration_lock = SPIN_LOCK_INIT;
/* Read IOAPIC */
static uint32_t amd64_ioapic_read (struct ioapic* ioapic, uint32_t reg) {
static uint32_t ioapic_read (struct ioapic* ioapic, uint32_t reg) {
spin_lock (&ioapic->lock);
*(volatile uint32_t*)ioapic->mmio_base = reg;
uint32_t ret = *(volatile uint32_t*)(ioapic->mmio_base + 0x10);
@@ -65,7 +65,7 @@ static uint32_t amd64_ioapic_read (struct ioapic* ioapic, uint32_t reg) {
}
/* Write IOAPIC */
static void amd64_ioapic_write (struct ioapic* ioapic, uint32_t reg, uint32_t value) {
static void ioapic_write (struct ioapic* ioapic, uint32_t reg, uint32_t value) {
spin_lock (&ioapic->lock);
*(volatile uint32_t*)ioapic->mmio_base = reg;
*(volatile uint32_t*)(ioapic->mmio_base + 0x10) = value;
@@ -73,12 +73,12 @@ static void amd64_ioapic_write (struct ioapic* ioapic, uint32_t reg, uint32_t va
}
/* Find an IOAPIC corresposting to provided IRQ */
static struct ioapic* amd64_ioapic_find (uint32_t irq) {
static struct ioapic* ioapic_find (uint32_t irq) {
struct ioapic* ioapic = NULL;
for (size_t i = 0; i < ioapic_entries; i++) {
ioapic = &ioapics[i];
uint32_t version = amd64_ioapic_read (ioapic, 1);
uint32_t version = ioapic_read (ioapic, 1);
uint32_t max = ((version >> 16) & 0xFF);
if ((irq >= ioapic->table_data.gsi_base) && (irq <= (ioapic->table_data.gsi_base + max)))
@@ -97,7 +97,7 @@ static struct ioapic* amd64_ioapic_find (uint32_t irq) {
* flags - IOAPIC redirection flags.
* lapic_id - Local APIC that will receive the interrupt.
*/
void amd64_ioapic_route_irq (uint32_t vec, uint32_t irq, uint64_t flags, uint64_t lapic_id) {
void ioapic_route_irq (uint32_t vec, uint32_t irq, uint64_t flags, uint64_t lapic_id) {
struct ioapic* ioapic = NULL;
struct acpi_madt_interrupt_source_override* override;
bool found_override = false;
@@ -121,7 +121,7 @@ void amd64_ioapic_route_irq (uint32_t vec, uint32_t irq, uint64_t flags, uint64_
uint32_t gsi = found_override ? override->gsi : irq;
ioapic = amd64_ioapic_find (gsi);
ioapic = ioapic_find (gsi);
DEBUG ("%p\n", ioapic);
if (ioapic == NULL)
@@ -129,12 +129,12 @@ void amd64_ioapic_route_irq (uint32_t vec, uint32_t irq, uint64_t flags, uint64_
uint32_t irq_reg = ((gsi - ioapic->table_data.gsi_base) * 2) + 0x10;
amd64_ioapic_write (ioapic, irq_reg + 1, (uint32_t)(calc_flags >> 32));
amd64_ioapic_write (ioapic, irq_reg, (uint32_t)calc_flags);
ioapic_write (ioapic, irq_reg + 1, (uint32_t)(calc_flags >> 32));
ioapic_write (ioapic, irq_reg, (uint32_t)calc_flags);
}
/* Find and initialize the IOAPIC */
void amd64_ioapic_init (void) {
void ioapic_init (void) {
struct limine_hhdm_response* hhdm = limine_hhdm_request.response;
struct uacpi_table apic_table;
@@ -176,41 +176,39 @@ void amd64_ioapic_init (void) {
}
/* Get MMIO base of Local APIC */
static uintptr_t amd64_lapic_base (void) { return thiscpu->lapic_mmio_base; }
static uintptr_t lapic_base (void) { return thiscpu->lapic_mmio_base; }
/* Write Local APIC */
static void amd64_lapic_write (uint32_t reg, uint32_t value) {
*(volatile uint32_t*)(amd64_lapic_base () + reg) = value;
static void lapic_write (uint32_t reg, uint32_t value) {
*(volatile uint32_t*)(lapic_base () + reg) = value;
}
/* Read Local APIC */
static uint32_t amd64_lapic_read (uint32_t reg) {
return *(volatile uint32_t*)(amd64_lapic_base () + reg);
}
static uint32_t lapic_read (uint32_t reg) { return *(volatile uint32_t*)(lapic_base () + reg); }
/* Get ID of Local APIC */
uint32_t amd64_lapic_id (void) { return amd64_lapic_read (LAPIC_ID) >> 24; }
uint32_t lapic_id (void) { return lapic_read (LAPIC_ID) >> 24; }
/* Send End of interrupt command to Local APIC */
void amd64_lapic_eoi (void) { amd64_lapic_write (LAPIC_EOI, 0); }
void lapic_eoi (void) { lapic_write (LAPIC_EOI, 0); }
/*
* Calibrate Local APIC to send interrupts in a set interval.
*
* us - Period length in microseconds
*/
static uint32_t amd64_lapic_calibrate (uint32_t us) {
static uint32_t lapic_calibrate (uint32_t us) {
spin_lock (&lapic_calibration_lock);
amd64_lapic_write (LAPIC_DCR, DIVIDER_VALUE);
lapic_write (LAPIC_DCR, DIVIDER_VALUE);
amd64_lapic_write (LAPIC_LVTTR, SCHED_PREEMPT_TIMER | (1 << 16));
amd64_lapic_write (LAPIC_TIMICT, 0xFFFFFFFF);
lapic_write (LAPIC_LVTTR, SCHED_PREEMPT_TIMER | (1 << 16));
lapic_write (LAPIC_TIMICT, 0xFFFFFFFF);
sleep_micro (us);
amd64_lapic_write (LAPIC_LVTTR, SCHED_PREEMPT_TIMER | (0 << 16));
uint32_t ticks = 0xFFFFFFFF - amd64_lapic_read (LAPIC_TIMCCT);
lapic_write (LAPIC_LVTTR, SCHED_PREEMPT_TIMER | (0 << 16));
uint32_t ticks = 0xFFFFFFFF - lapic_read (LAPIC_TIMCCT);
DEBUG ("timer ticks = %u\n", ticks);
spin_unlock (&lapic_calibration_lock);
@@ -223,30 +221,30 @@ static uint32_t amd64_lapic_calibrate (uint32_t us) {
*
* ticks - Initial tick count
*/
static void amd64_lapic_start (uint32_t ticks) {
amd64_lapic_write (LAPIC_DCR, DIVIDER_VALUE);
amd64_lapic_write (LAPIC_TIMICT, ticks);
amd64_lapic_write (LAPIC_LVTTR, SCHED_PREEMPT_TIMER | (1 << 17));
static void lapic_start (uint32_t ticks) {
lapic_write (LAPIC_DCR, DIVIDER_VALUE);
lapic_write (LAPIC_TIMICT, ticks);
lapic_write (LAPIC_LVTTR, SCHED_PREEMPT_TIMER | (1 << 17));
}
/*
* Initialize Local APIC, configure to send timer interrupts at a given period. See
* amd64_lapic_calibrate and amd64_lapic_start.
* lapic_calibrate and lapic_start.
*/
void amd64_lapic_init (uint32_t us) {
void lapic_init (uint32_t us) {
struct limine_hhdm_response* hhdm = limine_hhdm_request.response;
amd64_wrmsr (MSR_APIC_BASE, amd64_rdmsr (MSR_APIC_BASE) | (1 << 11));
wrmsr (MSR_APIC_BASE, rdmsr (MSR_APIC_BASE) | (1 << 11));
uintptr_t lapic_paddr = amd64_rdmsr (MSR_APIC_BASE) & 0xFFFFF000;
uintptr_t lapic_paddr = rdmsr (MSR_APIC_BASE) & 0xFFFFF000;
thiscpu->lapic_mmio_base = lapic_paddr + (uintptr_t)hhdm->offset;
mm_map_kernel_page (lapic_paddr, thiscpu->lapic_mmio_base, MM_PG_PRESENT | MM_PG_RW);
amd64_lapic_write (LAPIC_SIVR, 0xFF | (1 << 8));
lapic_write (LAPIC_SIVR, 0xFF | (1 << 8));
thiscpu->lapic_ticks = amd64_lapic_calibrate (us);
amd64_lapic_start (thiscpu->lapic_ticks);
thiscpu->lapic_ticks = lapic_calibrate (us);
lapic_start (thiscpu->lapic_ticks);
}
/*
@@ -255,12 +253,12 @@ void amd64_lapic_init (uint32_t us) {
* lapic_id - Target Local APIC
* vec - Interrupt vector/IDT stub, which will be invoked by the IPI.
*/
void amd64_lapic_ipi (uint32_t lapic_id, uint32_t vec) {
void lapic_ipi (uint32_t lapic_id, uint32_t vec) {
/* wait for previous IPI to finish */
while (amd64_lapic_read (LAPIC_ICR) & (1 << 12)) {
while (lapic_read (LAPIC_ICR) & (1 << 12)) {
__asm__ volatile ("pause");
}
amd64_lapic_write (LAPIC_ICR + 0x10, (lapic_id << 24));
amd64_lapic_write (LAPIC_ICR, vec);
lapic_write (LAPIC_ICR + 0x10, (lapic_id << 24));
lapic_write (LAPIC_ICR, vec);
}