Interrupt handling/cpu exceptions
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157
kernel/amd64/intr.c
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157
kernel/amd64/intr.c
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#include <libk/std.h>
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#include <libk/string.h>
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#include <sys/debug.h>
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#include <amd64/intr.h>
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#include <amd64/io.h>
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/* 8259 PIC defs. */
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#define PIC1 0x20
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#define PIC2 0xA0
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#define PIC1_CMD PIC1
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#define PIC1_DATA (PIC1 + 1)
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#define PIC2_CMD PIC2
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#define PIC2_DATA (PIC2 + 1)
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#define PIC_EOI 0x20
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#define ICW1_ICW4 0x01
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#define ICW1_SINGLE 0x02
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#define ICW1_INTVL4 0x04
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#define ICW1_LEVEL 0x08
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#define ICW1_INIT 0x10
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#define ICW4_8086 0x01
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#define ICW4_AUTO 0x02
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#define ICW4_BUFSLAVE 0x08
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#define ICW4_BUFMASER 0x0C
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#define ICW4_SFNM 0x10
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#define CASCADE_IRQ 2
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/* IDT defs. */
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#define IDT_ENTRIES_MAX 256
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struct idt_entry {
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uint16_t intrlow;
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uint16_t kernel_cs;
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uint8_t ist;
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uint8_t attrs;
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uint16_t intrmid;
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uint32_t intrhigh;
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uint32_t resv;
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} __attribute__((packed));
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struct idt {
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uint16_t limit;
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uint64_t base;
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} __attribute__((packed));
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__attribute__((aligned(16))) static volatile struct idt_entry idt_entries[IDT_ENTRIES_MAX];
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static volatile struct idt idt;
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extern void amd64_spin(void);
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/* Remaps and disables old 8259 PIC, since we'll be using APIC. */
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static void amd64_init_pic(void) {
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#define IO_OP(fn, ...) fn(__VA_ARGS__); amd64_io_wait()
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IO_OP(amd64_io_outb, PIC1_CMD, (ICW1_INIT | ICW1_ICW4));
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IO_OP(amd64_io_outb, PIC2_CMD, (ICW1_INIT | ICW1_ICW4));
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IO_OP(amd64_io_outb, PIC1_DATA, 0x20);
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IO_OP(amd64_io_outb, PIC2_DATA, 0x28);
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IO_OP(amd64_io_outb, PIC1_DATA, (1 << CASCADE_IRQ));
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IO_OP(amd64_io_outb, PIC2_DATA, 2);
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IO_OP(amd64_io_outb, PIC1_DATA, ICW4_8086);
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IO_OP(amd64_io_outb, PIC2_DATA, ICW4_8086);
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/* Disable */
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IO_OP(amd64_io_outb, PIC1_DATA, 0xFF);
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IO_OP(amd64_io_outb, PIC2_DATA, 0xFF);
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#undef IO_OP
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}
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static void amd64_idt_set(volatile struct idt_entry *ent, uint64_t handler, uint8_t flags) {
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ent->intrlow = (handler & 0xFFFF);
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ent->kernel_cs = 0x08; // GDT_KCODE (init.c)
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ent->ist = 0;
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ent->attrs = flags;
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ent->intrmid = ((handler >> 16) & 0xFFFF);
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ent->intrhigh = ((handler >> 32) & 0xFFFFFFFF);
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ent->resv = 0;
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}
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static void amd64_idt_init(void) {
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memset((void *)idt_entries, 0, sizeof(idt_entries));
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#define IDT_ENTRY(n) \
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extern void amd64_intr ## n(void); \
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amd64_idt_set(&idt_entries[(n)], (uint64_t)&amd64_intr ## n, 0x8E)
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IDT_ENTRY(0); IDT_ENTRY(1); IDT_ENTRY(2); IDT_ENTRY(3);
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IDT_ENTRY(4); IDT_ENTRY(5); IDT_ENTRY(6); IDT_ENTRY(7);
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IDT_ENTRY(8); IDT_ENTRY(9); IDT_ENTRY(10); IDT_ENTRY(11);
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IDT_ENTRY(12); IDT_ENTRY(13); IDT_ENTRY(14); IDT_ENTRY(15);
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IDT_ENTRY(16); IDT_ENTRY(17); IDT_ENTRY(18); IDT_ENTRY(19);
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IDT_ENTRY(20); IDT_ENTRY(21); IDT_ENTRY(22); IDT_ENTRY(23);
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IDT_ENTRY(24); IDT_ENTRY(25); IDT_ENTRY(26); IDT_ENTRY(27);
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IDT_ENTRY(28); IDT_ENTRY(29); IDT_ENTRY(30); IDT_ENTRY(31);
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IDT_ENTRY(32); IDT_ENTRY(33); IDT_ENTRY(34); IDT_ENTRY(35);
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IDT_ENTRY(36); IDT_ENTRY(37); IDT_ENTRY(38); IDT_ENTRY(39);
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IDT_ENTRY(40); IDT_ENTRY(41); IDT_ENTRY(42); IDT_ENTRY(43);
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IDT_ENTRY(44); IDT_ENTRY(45); IDT_ENTRY(46); IDT_ENTRY(47);
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#undef IDT_ENTRY
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idt.limit = sizeof(idt_entries) - 1;
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idt.base = (uint64_t)idt_entries;
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__asm__ volatile("lidt %0" :: "m"(idt));
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__asm__ volatile("sti");
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}
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static void amd64_intr_exception(struct saved_regs *regs) {
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DEBUG("cpu exception %lu (%lu)\n", regs->trap, regs->error);
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uint64_t cr2;
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__asm__ volatile("movq %%cr2, %0" : "=r"(cr2));
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uint64_t cr3;
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__asm__ volatile("movq %%cr3, %0" : "=r"(cr3));
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debugprintf(
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"r15=%016lx r14=%016lx r13=%016lx\n"
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"r12=%016lx r11=%016lx r10=%016lx\n"
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"r9 =%016lx r8 =%016lx rbp=%016lx\n"
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"rdi=%016lx rsi=%016lx rdx=%016lx\n"
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"rcx=%016lx rax=%016lx trp=%016lx\n"
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"err=%016lx rip=%016lx cs =%016lx\n"
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"rfl=%016lx rsp=%016lx ss =%016lx\n"
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"cr2=%016lx cr3=%016lx rbx=%016lx\n",
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regs->r15, regs->r14, regs->r13,
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regs->r12, regs->r11, regs->r10,
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regs->r9, regs->r8, regs->rbp,
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regs->rdi, regs->rsi, regs->rdx,
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regs->rcx, regs->rax, regs->trap,
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regs->error, regs->rip, regs->cs,
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regs->rflags, regs->rsp, regs->ss,
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cr2, cr3, regs->rbx
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);
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amd64_spin();
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}
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void amd64_intr_handler(void *stack_ptr) {
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struct saved_regs *regs = stack_ptr;
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if (regs->trap <= 31) {
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amd64_intr_exception(regs);
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} else {
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DEBUG("unknown trap %lu\n", regs->trap);
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}
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}
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void amd64_intr_init(void) {
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amd64_init_pic();
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amd64_idt_init();
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}
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