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Remove Doxygen-style comments, change formatting to wrap comments
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This commit is contained in:
Kamil Kowalczyk
2026-01-06 02:04:32 +01:00
parent 902682ac11
commit 7915986902
15 changed files with 469 additions and 510 deletions
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2
.clang-format
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@@ -50,7 +50,7 @@ AlignOperands: false
SortIncludes: true
# Comments
ReflowComments: false
ReflowComments: true
CommentPragmas: '^ IWYU pragma:'
# Misc

103
kernel/amd64/apic.c
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@@ -16,49 +16,49 @@
#define IOAPICS_MAX 24
#define INTERRUPT_SRC_OVERRIDES_MAX 24
/// ID of Local APIC
/* ID of Local APIC */
#define LAPIC_ID 0x20
/// End of interrupt register
/* End of interrupt register */
#define LAPIC_EOI 0xB0
/// Spurious interrupt vector register
/* Spurious interrupt vector register */
#define LAPIC_SIVR 0xF0
/// Interrupt command register
/* Interrupt command register */
#define LAPIC_ICR 0x300
/// LVT timer register
/* LVT timer register */
#define LAPIC_LVTTR 0x320
/// Timer initial count register
/* Timer initial count register */
#define LAPIC_TIMICT 0x380
/// Timer current count register
/* Timer current count register */
#define LAPIC_TIMCCT 0x390
/// Divide config register
/* Divide config register */
#define LAPIC_DCR 0x3E0
/// Table of IOAPICS
/* Table of IOAPICS */
static struct acpi_madt_ioapic apics[IOAPICS_MAX];
/* Table of interrupt source overrides */
/* clang-format off */
/// Table of interrupt source overrides
static struct acpi_madt_interrupt_source_override intr_src_overrides[INTERRUPT_SRC_OVERRIDES_MAX];
/* clang-format on */
/// Count of actual IOAPIC entries
/* Count of actual IOAPIC entries */
static size_t ioapic_entries = 0;
/// Count of actual interrupt source overrides
/* Count of actual interrupt source overrides */
static size_t intr_src_override_entries = 0;
/// Local APIC MMIO base address. It comes from MSR_APIC_BASE
/* Local APIC MMIO base address. It comes from MSR_APIC_BASE */
static uintptr_t lapic_mmio_base = 0;
/// Read IOAPIC
/* Read IOAPIC */
static uint32_t amd64_ioapic_read (uintptr_t vaddr, uint32_t reg) {
*(volatile uint32_t*)vaddr = reg;
return *(volatile uint32_t*)(vaddr + 0x10);
}
/// Write IOAPIC
/* Write IOAPIC */
static void amd64_ioapic_write (uintptr_t vaddr, uint32_t reg, uint32_t value) {
*(volatile uint32_t*)vaddr = reg;
*(volatile uint32_t*)(vaddr + 0x10) = value;
}
/// Find an IOAPIC corresposting to provided IRQ
/* Find an IOAPIC corresposting to provided IRQ */
static struct acpi_madt_ioapic* amd64_ioapic_find (uint8_t irq) {
struct acpi_madt_ioapic* apic = NULL;
struct limine_hhdm_response* hhdm = limine_hhdm_request.response;
@@ -75,21 +75,14 @@ static struct acpi_madt_ioapic* amd64_ioapic_find (uint8_t irq) {
return NULL;
}
/**
* @brief Route IRQ to an IDT entry of a given Local APIC.
/*
* Route IRQ to an IDT entry of a given Local APIC.
*
* @param vec
* Interrupt vector number, which will be delivered to the CPU
*
* @param irq
* Legacy IRQ number to be routed. Can be changed by an interrupt source override
* vec - Interrupt vector number, which will be delivered to the CPU.
* irq -Legacy IRQ number to be routed. Can be changed by an interrupt source override
* into a different GSI.
*
* @param flags
* IOAPIC redirection flags.
*
* @param lapic_id
* Local APIC that will receive the interrupt.
* flags - IOAPIC redirection flags.
* lapic_id - Local APIC that will receive the interrupt.
*/
void amd64_ioapic_route_irq (uint8_t vec, uint8_t irq, uint64_t flags, uint64_t lapic_id) {
struct acpi_madt_ioapic* apic = NULL;
@@ -132,7 +125,7 @@ void amd64_ioapic_route_irq (uint8_t vec, uint8_t irq, uint64_t flags, uint64_t
(uint32_t)(calc_flags >> 32));
}
/// Mask a given IRQ
/* Mask a given IRQ */
void amd64_ioapic_mask (uint8_t irq) {
struct acpi_madt_ioapic* apic;
struct limine_hhdm_response* hhdm = limine_hhdm_request.response;
@@ -149,7 +142,7 @@ void amd64_ioapic_mask (uint8_t irq) {
value | (1 << 16));
}
/// Unmask a given IRQ
/* Unmask a given IRQ */
void amd64_ioapic_unmask (uint8_t irq) {
struct acpi_madt_ioapic* apic;
struct limine_hhdm_response* hhdm = limine_hhdm_request.response;
@@ -166,7 +159,7 @@ void amd64_ioapic_unmask (uint8_t irq) {
value & ~(1 << 16));
}
/// Find and initialize the IOAPIC
/* Find and initialize the IOAPIC */
void amd64_ioapic_init (void) {
struct limine_hhdm_response* hhdm = limine_hhdm_request.response;
@@ -204,35 +197,32 @@ void amd64_ioapic_init (void) {
}
}
/// Get MMIO base of Local APIC
/* Get MMIO base of Local APIC */
static uintptr_t amd64_lapic_base (void) { return lapic_mmio_base; }
/// Write Local APIC
/* Write Local APIC */
static void amd64_lapic_write (uint32_t reg, uint32_t value) {
*(volatile uint32_t*)(amd64_lapic_base () + reg) = value;
}
/// Read Local APIC
/* Read Local APIC */
static uint32_t amd64_lapic_read (uint32_t reg) {
return *(volatile uint32_t*)(amd64_lapic_base () + reg);
}
/// Get ID of Local APIC
/* Get ID of Local APIC */
uint32_t amd64_lapic_id (void) { return amd64_lapic_read (LAPIC_ID) >> 24; }
/// Send End of interrupt command to Local APIC
/* Send End of interrupt command to Local APIC */
void amd64_lapic_eoi (void) { amd64_lapic_write (LAPIC_EOI, 0); }
/// Set initial counter value in Local APIC timer
/* Set initial counter value in Local APIC timer */
void amd64_lapic_tick (uint32_t tick) { amd64_lapic_write (LAPIC_TIMICT, tick); }
/**
* @brief Calibrate Local APIC to send interrupts in a set interval.
/*
* Calibrate Local APIC to send interrupts in a set interval.
*
* @param us
* Period length in microseconds
*
* @return amount of ticsk in a given period
* us - Period length in microseconds
*/
static uint32_t amd64_lapic_calibrate (uint32_t us) {
amd64_lapic_write (LAPIC_DCR, 0x0B);
@@ -248,12 +238,10 @@ static uint32_t amd64_lapic_calibrate (uint32_t us) {
return ticks;
}
/**
* @brief Starts a Local APIC, configures LVT timer to
* send interrupts at \ref SCHED_PREEMPT_TIMER.
/*
* Starts a Local APIC, configures LVT timer to send interrupts at SCHED_PREEMPT_TIMER.
*
* @param ticks
* Initial tick count
* ticks - Initial tick count
*/
static void amd64_lapic_start (uint32_t ticks) {
amd64_lapic_write (LAPIC_DCR, 0x0B);
@@ -263,9 +251,9 @@ static void amd64_lapic_start (uint32_t ticks) {
amd64_lapic_write (LAPIC_TIMICT, ticks);
}
/**
* @brief Initialize Local APIC, configure to send timer interrupts
* at a given period. See \ref amd64_lapic_calibrate and \ref amd64_lapic_start.
/*
* Initialize Local APIC, configure to send timer interrupts at a given period. See
* amd64_lapic_calibrate and amd64_lapic_start.
*/
uint64_t amd64_lapic_init (uint32_t us) {
struct limine_hhdm_response* hhdm = limine_hhdm_request.response;
@@ -287,14 +275,11 @@ uint64_t amd64_lapic_init (uint32_t us) {
return ticks;
}
/**
* @brief Send an IPI to a given Local APIC. This till invoke an IDT stub located at vec.
/*
* Send an IPI to a given Local APIC. This till invoke an IDT stub located at vec.
*
* @param lapic_id
* Target Local APIC
*
* @param vec
* Interrupt vector/IDT stub, which will be invoked by the IPI.
* lapic_id - Target Local APIC
* vec - Interrupt vector/IDT stub, which will be invoked by the IPI.
*/
void amd64_lapic_ipi (uint8_t lapic_id, uint8_t vec) {
amd64_lapic_write (LAPIC_ICR + 0x10, (lapic_id << 24));

11
kernel/amd64/bootmain.c
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@@ -1,5 +1,3 @@
/** @file */
#include <amd64/apic.h>
#include <amd64/debug.h>
#include <amd64/hpet.h>
@@ -24,14 +22,11 @@
#define UACPI_MEMORY_BUFFER_MAX 4096
/** @cond DOXYGEN_IGNORE */
ALIGNED (16) static uint8_t uacpi_memory_buffer[UACPI_MEMORY_BUFFER_MAX];
/** @endcond */
/**
* @brief The kernel starts booting here. This is the entry point after
* Limine hands control. We set up all the necessary platform-dependent
* subsystems/drivers and jump into the init app.
/*
* The kernel starts booting here. This is the entry point after Limine hands control. We set up all
* the necessary platform-dependent subsystems/drivers and jump into the init app.
*/
void bootmain (void) {
struct cpu* bsp_cpu = cpu_make ();

21
kernel/amd64/debug.c
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@@ -6,30 +6,33 @@
#include <sync/spin_lock.h>
#include <sys/debug.h>
/// Port for printing to serial
/* Port for printing to serial */
/* TODO: Make this configurable */
#define PORT_COM1 0x03F8
/// \ref debugprintf buffer size
/* debugprintf buffer size */
#define BUFFER_SIZE 1024
/// Lock, which ensures that prints to the serial port are atomic
/*
* Lock, which ensures that prints to the serial port are atomic (ie. one debugprintf is atomic in
* itself).
*/
static spin_lock_t serial_lock = SPIN_LOCK_INIT;
static bool debug_init = false;
/// Block until TX buffer is empty
/* Block until TX buffer is empty */
static bool amd64_debug_serial_tx_empty (void) {
return (bool)(amd64_io_inb (PORT_COM1 + 5) & 0x20);
}
/// Write a single character to serial
/* Write a single character to serial */
static void amd64_debug_serial_write (char x) {
while (!amd64_debug_serial_tx_empty ())
;
amd64_io_outb (PORT_COM1, (uint8_t)x);
}
/**
* @brief Formatted printing to serial. \ref serial_lock ensures that
* all prints are atomic.
/*
* Formatted printing to serial. serial_lock ensures that all prints are atomic.
*/
void debugprintf (const char* fmt, ...) {
if (!debug_init)
@@ -57,7 +60,7 @@ void debugprintf (const char* fmt, ...) {
spin_unlock (&serial_lock);
}
/// Initialize serial
/* Initialize serial */
void amd64_debug_init (void) {
amd64_io_outb (PORT_COM1 + 1, 0x00);
amd64_io_outb (PORT_COM1 + 3, 0x80);

10
kernel/amd64/gdt.h
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@@ -11,13 +11,11 @@
#define GDT_UDATA 0x20
#define GDT_TSS 0x28
/// Size of kernel stack
/* Size of kernel stack */
#define KSTACK_SIZE (32 * 1024)
/**
* @file
*
* @brief 64-bit GDT structure. For more info see:
/*
* 64-bit GDT structure. For more info see:
* - https://wiki.osdev.org/Global_Descriptor_Table
* - https://wiki.osdev.org/GDT_Tutorial
*/
@@ -31,11 +29,13 @@ struct gdt_entry {
uint8_t basehigh;
} PACKED;
/* Struct that gets loaded into GDTR */
struct gdt_ptr {
uint16_t limit;
uint64_t base;
} PACKED;
/* New, extended GDT (we need to extend Limine's GDT) */
struct gdt_extended {
struct gdt_entry old[5];
struct gdt_entry tsslow;

32
kernel/amd64/hpet.c
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@@ -10,30 +10,27 @@
#include <uacpi/tables.h>
#include <uacpi/uacpi.h>
/**
* @file
*
* @brief HPET (High Precision Event Timer) driver code.
* See more at https://wiki.osdev.org/HPET
/*
* HPET (High Precision Event Timer) driver code. See more at https://wiki.osdev.org/HPET
*/
/// HPET Main Counter Value Register
/* HPET Main Counter Value Register */
#define HPET_MCVR 0xF0
/// HPET General Configuration Register
/* HPET General Configuration Register */
#define HPET_GCR 0x10
/// HPET General Capabilities and ID Register
/* HPET General Capabilities and ID Register */
#define HPET_GCIDR 0x00
/// Set whether we sould use 32-bit or 64-bit reads/writes
/* Set whether we sould use 32-bit or 64-bit reads/writes */
static bool hpet_32bits = 1;
/// Physical address for HPET MMIO
/* Physical address for HPET MMIO */
static uintptr_t hpet_paddr;
/// HPET period in femtoseconds
/* HPET period in femtoseconds */
static uint64_t hpet_period_fs;
/// Lock, which protects concurrent access. See \ref amd64/smp.c
/* Lock, which protects concurrent access. See amd64/smp.c */
static spin_lock_t hpet_lock = SPIN_LOCK_INIT;
/// Read a HPET register. Assumes caller holds \ref hpet_lock
/* Read a HPET register. Assumes caller holds \ref hpet_lock */
static uint64_t amd64_hpet_read (uint32_t reg) {
struct limine_hhdm_response* hhdm = limine_hhdm_request.response;
uintptr_t hpet_vaddr = hpet_paddr + (uintptr_t)hhdm->offset;
@@ -41,7 +38,7 @@ static uint64_t amd64_hpet_read (uint32_t reg) {
: *(volatile uint64_t*)(hpet_vaddr + reg));
}
/// Write a HPET register. Assumes caller holds \ref hpet_lock
/* Write a HPET register. Assumes caller holds \ref hpet_lock */
static void amd64_hpet_write (uint32_t reg, uint64_t value) {
struct limine_hhdm_response* hhdm = limine_hhdm_request.response;
uintptr_t hpet_vaddr = hpet_paddr + (uintptr_t)hhdm->offset;
@@ -51,10 +48,11 @@ static void amd64_hpet_write (uint32_t reg, uint64_t value) {
*(volatile uint64_t*)(hpet_vaddr + reg) = value;
}
/// Read current value of \ref HPET_MCVR register.
/* Read current value of \ref HPET_MCVR register. */
static uint64_t amd64_hpet_timestamp (void) { return amd64_hpet_read (HPET_MCVR); }
/// Sleep for a given amount of microseconds. This time can last longer due to \ref hpet_lock being held.
/* Sleep for a given amount of microseconds. This time can last longer due to \ref hpet_lock being
* held. */
void amd64_hpet_sleep_micro (uint64_t us) {
spin_lock (&hpet_lock);
@@ -74,7 +72,7 @@ void amd64_hpet_sleep_micro (uint64_t us) {
spin_unlock (&hpet_lock);
}
/// Initialize HPET
/* Initialize HPET */
void amd64_hpet_init (void) {
struct uacpi_table hpet_table;
uacpi_status status = uacpi_table_find_by_signature (ACPI_HPET_SIGNATURE, &hpet_table);

13
kernel/amd64/init.c
View File

@@ -9,7 +9,7 @@
#define TSS 0x80
#define TSS_PRESENT 0x89
/// Set a GDT entry
/* Set a GDT entry */
static void amd64_gdt_set (volatile struct gdt_entry* ent, uint32_t base, uint32_t limit,
uint8_t acc, uint8_t gran) {
ent->baselow = (base & 0xFFFF);
@@ -20,7 +20,7 @@ static void amd64_gdt_set (volatile struct gdt_entry* ent, uint32_t base, uint32
ent->access = acc;
}
/// Initialize GDT and TSS structures for a given CPU
/* Initialize GDT and TSS structures for a given CPU */
static void amd64_gdt_init (struct cpu* cpu) {
volatile struct tss* tss = &cpu->tss;
volatile struct gdt_extended* gdt = &cpu->gdt;
@@ -51,11 +51,13 @@ static void amd64_gdt_init (struct cpu* cpu) {
gdt->tsshigh.access = 0;
gdt->tsshigh.gran = 0;
/* Load GDTR */
struct gdt_ptr gdtr;
gdtr.limit = sizeof (*gdt) - 1;
gdtr.base = (uint64_t)gdt;
__asm__ volatile ("lgdt %0" ::"m"(gdtr) : "memory");
/* Reload CS */
__asm__ volatile ("pushq %[kcode]\n"
"lea 1f(%%rip), %%rax\n"
"pushq %%rax\n"
@@ -72,11 +74,10 @@ static void amd64_gdt_init (struct cpu* cpu) {
__asm__ volatile ("ltr %0" ::"r"((uint16_t)GDT_TSS));
}
/**
* @brief Initialize essentials (GDT, TSS, IDT) for a given CPU
/*
* Initialize essentials (GDT, TSS, IDT) for a given CPU
*
* @param load_idt
* Tell whether the IDT needs to be loaded. It only has to be loaded once on
* load_idt - Tell whether the IDT needs to be loaded. It only has to be loaded once on
* the BSP
*/
void amd64_init (struct cpu* cpu, bool load_idt) {

38
kernel/amd64/intr.c
View File

@@ -39,7 +39,7 @@
#define IDT_ENTRIES_MAX 256
/// 64-bit <IDT entry structure: https://wiki.osdev.org/Interrupt_Descriptor_Table
/* 64-bit <IDT entry structure: https://wiki.osdev.org/Interrupt_Descriptor_Table */
struct idt_entry {
uint16_t intrlow;
uint16_t kernel_cs;
@@ -55,18 +55,14 @@ struct idt {
uint64_t base;
} PACKED;
/** @cond DOXYGEN_IGNORE */
ALIGNED (16) static volatile struct idt_entry idt_entries[IDT_ENTRIES_MAX];
/** @endcond */
static volatile struct idt idt;
/// Remaps and disables old 8259 PIC, since we'll be using APIC.
/* Remaps and disables old 8259 PIC, since we'll be using APIC. */
static void amd64_init_pic (void) {
/** @cond DOXYGEN_IGNORE */
#define IO_OP(fn, ...) \
fn (__VA_ARGS__); \
amd64_io_wait ()
/** @endcond */
IO_OP (amd64_io_outb, PIC1_CMD, (ICW1_INIT | ICW1_ICW4));
IO_OP (amd64_io_outb, PIC2_CMD, (ICW1_INIT | ICW1_ICW4));
@@ -87,7 +83,7 @@ static void amd64_init_pic (void) {
#undef IO_OP
}
/// Set IDT entry
/* Set IDT entry */
static void amd64_idt_set (volatile struct idt_entry* ent, uint64_t handler, uint8_t flags,
uint8_t ist) {
ent->intrlow = (handler & 0xFFFF);
@@ -99,18 +95,16 @@ static void amd64_idt_set (volatile struct idt_entry* ent, uint64_t handler, uin
ent->resv = 0;
}
/// Load the IDT
/* Load the IDT */
void amd64_load_idt (void) { __asm__ volatile ("lidt %0" ::"m"(idt)); }
/// Initialize IDT entries
/* Initialize IDT entries */
static void amd64_idt_init (void) {
memset ((void*)idt_entries, 0, sizeof (idt_entries));
/** @cond DOXYGEN_IGNORE */
#define IDT_ENTRY(n, ist) \
extern void amd64_intr##n (void); \
amd64_idt_set (&idt_entries[(n)], (uint64_t)&amd64_intr##n, 0x8E, (ist))
/** @endcond */
/* clang-format off */
IDT_ENTRY (0, 0); IDT_ENTRY (1, 0); IDT_ENTRY (2, 0); IDT_ENTRY (3, 0);
IDT_ENTRY (4, 0); IDT_ENTRY (5, 0); IDT_ENTRY (6, 0); IDT_ENTRY (7, 0);
@@ -136,13 +130,7 @@ static void amd64_idt_init (void) {
amd64_load_idt ();
}
/**
* @brief Handle CPU exception and dump registers. If incoming CS has CPL3, kill the
* process.
*
* @param regs
* saved registers
*/
/* Handle CPU exception and dump registers. If incoming CS has CPL3, kill the process. */
static void amd64_intr_exception (struct saved_regs* regs) {
DEBUG ("cpu exception %lu (%lu)\n", regs->trap, regs->error);
@@ -171,7 +159,7 @@ static void amd64_intr_exception (struct saved_regs* regs) {
}
}
/// Handle incoming interrupt, dispatch IRQ handlers.
/* Handle incoming interrupt, dispatch IRQ handlers. */
void amd64_intr_handler (void* stack_ptr) {
struct saved_regs* regs = stack_ptr;
@@ -194,7 +182,7 @@ void amd64_intr_handler (void* stack_ptr) {
}
}
/// Initialize interrupts
/* Initialize interrupts */
void amd64_intr_init (void) {
amd64_init_pic ();
amd64_idt_init ();
@@ -202,34 +190,34 @@ void amd64_intr_init (void) {
/* Aux. */
/// Save RFLAGS of the current CPU
/* Save RFLAGS of the current CPU */
static uint64_t amd64_irq_save_flags (void) {
uint64_t rflags;
__asm__ volatile ("pushfq; cli; popq %0" : "=r"(rflags)::"memory", "cc");
return rflags;
}
/// Restore interrupts (IF bit) from RFLAGS
/* Restore interrupts (IF bit) from RFLAGS */
static void amd64_irq_restore_flags (uint64_t rflags) {
if (rflags & (1ULL << 9))
__asm__ volatile ("sti");
}
/// Save current interrupt state
/* Save current interrupt state */
void irq_save (void) {
int prev = atomic_fetch_add_explicit (&thiscpu->irq_ctx.nesting, 1, memory_order_acq_rel);
if (prev == 0)
thiscpu->irq_ctx.rflags = amd64_irq_save_flags ();
}
/// Restore interrupt state
/* Restore interrupt state */
void irq_restore (void) {
int prev = atomic_fetch_sub_explicit (&thiscpu->irq_ctx.nesting, 1, memory_order_acq_rel);
if (prev == 1)
amd64_irq_restore_flags (thiscpu->irq_ctx.rflags);
}
/// Map custom IRQ mappings to legacy IRQs
/* Map custom IRQ mappings to legacy IRQs */
uint8_t amd64_resolve_irq (uint8_t irq) {
static const uint8_t mappings[] = {
[SCHED_PREEMPT_TIMER] = 0,

7
kernel/amd64/intr_defs.h
View File

@@ -1,11 +1,8 @@
#ifndef _KERNEL_AMD64_INTR_DEFS_H
#define _KERNEL_AMD64_INTR_DEFS_H
/**
* @file
* Definitions for custom, nonstandard IDT entries. They have to be remapped
* by \ref amd64_resolve_irq into legacy IRQs.
*/
/* Definitions for custom, nonstandard IDT entries. They have to be remapped by amd64_resolve_irq
* into legacy IRQs. */
#define SCHED_PREEMPT_TIMER 80
#define TLB_SHOOTDOWN 81

56
kernel/amd64/mm.c
View File

@@ -11,36 +11,36 @@
#include <sys/mm.h>
#include <sys/smp.h>
/// Present flag
/* Present flag */
#define AMD64_PG_PRESENT (1 << 0)
/// Writable flag
/* Writable flag */
#define AMD64_PG_RW (1 << 1)
/// User-accessible flag
/* User-accessible flag */
#define AMD64_PG_USER (1 << 2)
/// Auxilary struct for page directory walking
/* Auxilary struct for page directory walking */
struct pg_index {
uint16_t pml4, pml3, pml2, pml1;
} PACKED;
/// Kernel page directory
/* Kernel page directory */
static struct pd kernel_pd = {.lock = SPIN_LOCK_INIT};
/// Lock needed to sync between map/unmap operations and TLB shootdown
/* Lock needed to sync between map/unmap operations and TLB shootdown */
static spin_lock_t mm_lock = SPIN_LOCK_INIT;
/// Get current value of CR3 register
/* Get current value of CR3 register */
static uintptr_t amd64_current_cr3 (void) {
uintptr_t cr3;
__asm__ volatile ("movq %%cr3, %0" : "=r"(cr3)::"memory");
return cr3;
}
/// Load kernel CR3 as current CR3
/* Load kernel CR3 as current CR3 */
void amd64_load_kernel_cr3 (void) {
__asm__ volatile ("movq %0, %%cr3" ::"r"(kernel_pd.cr3_paddr) : "memory");
}
/// Extract PML info from virtual address
/* Extract PML info from virtual address */
static struct pg_index amd64_mm_page_index (uint64_t vaddr) {
struct pg_index ret;
@@ -52,7 +52,7 @@ static struct pg_index amd64_mm_page_index (uint64_t vaddr) {
return ret;
}
/// Walk paging tables and allocate necessary structures along the way
/* Walk paging tables and allocate necessary structures along the way */
static uint64_t* amd64_mm_next_table (uint64_t* table, uint64_t entry_idx, bool alloc) {
uint64_t entry = table[entry_idx];
physaddr_t paddr;
@@ -85,7 +85,7 @@ static bool amd64_mm_is_table_empty (uint64_t* table) {
return true;
}
/// Convert generic memory management subsystem flags into AMD64-specific flags
/* Convert generic memory management subsystem flags into AMD64-specific flags */
static uint64_t amd64_mm_resolve_flags (uint32_t generic) {
uint64_t flags = 0;
@@ -96,16 +96,13 @@ static uint64_t amd64_mm_resolve_flags (uint32_t generic) {
return flags;
}
/// Reload the current CR3 value ON A LOCAL CPU
/* Reload the current CR3 value ON A LOCAL CPU */
static void amd64_reload_cr3 (void) {
uint64_t cr3;
__asm__ volatile ("movq %%cr3, %0; movq %0, %%cr3" : "=r"(cr3)::"memory");
}
/**
* @brief Map physical address to virtual address with flags. TLB needs to be flushed
* afterwards.
*/
/* Map physical address to virtual address with flags. TLB needs to be flushed afterwards. */
void mm_map_page (struct pd* pd, uintptr_t paddr, uintptr_t vaddr, uint32_t flags) {
spin_lock (&mm_lock);
@@ -147,12 +144,12 @@ done:
spin_unlock (&mm_lock);
}
/// Map a page into kernel page directory
/* Map a page into kernel page directory */
void mm_map_kernel_page (uintptr_t paddr, uintptr_t vaddr, uint32_t flags) {
mm_map_page (&kernel_pd, paddr, vaddr, flags);
}
/// Unmap a virtual address. TLB needs to be flushed afterwards
/* Unmap a virtual address. TLB needs to be flushed afterwards */
void mm_unmap_page (struct pd* pd, uintptr_t vaddr, uint32_t flags) {
spin_lock (&mm_lock);
@@ -212,18 +209,18 @@ done:
spin_unlock (&mm_lock);
}
/// Unmap a page from kernel page directory
/* Unmap a page from kernel page directory */
void mm_unmap_kernel_page (uintptr_t vaddr, uint32_t flags) {
mm_unmap_page (&kernel_pd, vaddr, flags);
}
/// Lock kernel page directory
/* Lock kernel page directory */
void mm_lock_kernel (void) { spin_lock (&kernel_pd.lock); }
/// Unlock kernel page directory
/* Unlock kernel page directory */
void mm_unlock_kernel (void) { spin_unlock (&kernel_pd.lock); }
/// Allocate a userspace-ready page directory
/* Allocate a userspace-ready page directory */
uintptr_t mm_alloc_user_pd_phys (void) {
struct limine_hhdm_response* hhdm = limine_hhdm_request.response;
@@ -241,10 +238,7 @@ uintptr_t mm_alloc_user_pd_phys (void) {
return cr3;
}
/**
* @brief Reload after map/unmap operation was performed. This function does the TLB
* shootdown.
*/
/* Reload after map/unmap operation was performed. This function does the TLB shootdown. */
void mm_reload (void) {
spin_lock (&mm_lock);
@@ -257,7 +251,7 @@ void mm_reload (void) {
spin_unlock (&mm_lock);
}
/// TLB shootdown IRQ handler
/* TLB shootdown IRQ handler */
static void amd64_tlb_shootdown_irq (void* arg, void* regs) {
(void)arg, (void)regs;
@@ -265,13 +259,11 @@ static void amd64_tlb_shootdown_irq (void* arg, void* regs) {
DEBUG ("cpu %u TLB shootdown\n", thiscpu->id);
}
/**
* @brief Continue initializing memory management subsystem for AMD64 after the
* essential parts were initialized
*/
/* Continue initializing memory management subsystem for AMD64 after the essential parts were
* initialized */
void mm_init2 (void) {
irq_attach (&amd64_tlb_shootdown_irq, NULL, TLB_SHOOTDOWN, IRQ_INTERRUPT_SAFE);
}
/// Initialize essentials for the AMD64 memory management subsystem
/* Initialize essentials for the AMD64 memory management subsystem */
void mm_init (void) { kernel_pd.cr3_paddr = amd64_current_cr3 (); }

10
kernel/amd64/msr-index.h
View File

@@ -85,7 +85,7 @@ patent must be licensed for everyone's free use or not licensed at all.
The precise terms and conditions for copying, distribution and
modification follow.
GNU GENERAL PUBLIC LICENSE
TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION
@@ -140,7 +140,7 @@ above, provided that you also meet all of these conditions:
License. (Exception: if the Program itself is interactive but
does not normally print such an announcement, your work based on
the Program is not required to print an announcement.)
These requirements apply to the modified work as a whole. If
identifiable sections of that work are not derived from the Program,
and can be reasonably considered independent and separate works in
@@ -198,7 +198,7 @@ access to copy from a designated place, then offering equivalent
access to copy the source code from the same place counts as
distribution of the source code, even though third parties are not
compelled to copy the source along with the object code.
4. You may not copy, modify, sublicense, or distribute the Program
except as expressly provided under this License. Any attempt
otherwise to copy, modify, sublicense or distribute the Program is
@@ -255,7 +255,7 @@ impose that choice.
This section is intended to make thoroughly clear what is believed to
be a consequence of the rest of this License.
8. If the distribution and/or use of the Program is restricted in
certain countries either by patents or by copyrighted interfaces, the
original copyright holder who places the Program under this License
@@ -308,7 +308,7 @@ PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE
POSSIBILITY OF SUCH DAMAGES.
END OF TERMS AND CONDITIONS
How to Apply These Terms to Your New Programs
If you develop a new program, and you want it to be of the greatest

318
kernel/aux/elf.h
View File

@@ -391,10 +391,10 @@ typedef struct {
#define SHN_LORESERVE 0xff00 /* Start of reserved indices */
#define SHN_LOPROC 0xff00 /* Start of processor-specific */
#define SHN_BEFORE \
0xff00 /* Order section before all others
0xff00 /* Order section before all others \
(Solaris). */
#define SHN_AFTER \
0xff01 /* Order section after all others
0xff01 /* Order section after all others \
(Solaris). */
#define SHN_HIPROC 0xff1f /* End of processor-specific */
#define SHN_LOOS 0xff20 /* Start of OS-specific */
@@ -454,7 +454,7 @@ typedef struct {
#define SHF_INFO_LINK (1 << 6) /* `sh_info' contains SHT index */
#define SHF_LINK_ORDER (1 << 7) /* Preserve order after combining */
#define SHF_OS_NONCONFORMING \
(1 << 8) /* Non-standard OS specific handling
(1 << 8) /* Non-standard OS specific handling \
required */
#define SHF_GROUP (1 << 9) /* Section is member of a group. */
#define SHF_TLS (1 << 10) /* Section hold thread-local data. */
@@ -463,10 +463,10 @@ typedef struct {
#define SHF_MASKPROC 0xf0000000 /* Processor-specific */
#define SHF_GNU_RETAIN (1 << 21) /* Not to be GCed by linker. */
#define SHF_ORDERED \
(1 << 30) /* Special ordering requirement
(1 << 30) /* Special ordering requirement \
(Solaris). */
#define SHF_EXCLUDE \
(1U << 31) /* Section is excluded unless
(1U << 31) /* Section is excluded unless \
referenced or allocated (Solaris).*/
/* Section compression header. Used when SHF_COMPRESSED is set. */
@@ -538,7 +538,7 @@ typedef struct {
#define SYMINFO_FLG_PASSTHRU 0x0002 /* Pass-through symbol for translator */
#define SYMINFO_FLG_COPY 0x0004 /* Symbol is a copy-reloc */
#define SYMINFO_FLG_LAZYLOAD \
0x0008 /* Symbol bound to object to be lazy
0x0008 /* Symbol bound to object to be lazy \
loaded */
/* Syminfo version values. */
#define SYMINFO_NONE 0
@@ -716,7 +716,7 @@ typedef struct {
#define NT_PRSTATUS 1 /* Contains copy of prstatus struct */
#define NT_PRFPREG \
2 /* Contains copy of fpregset
2 /* Contains copy of fpregset \
struct. */
#define NT_FPREGSET 2 /* Contains copy of fpregset struct */
#define NT_PRPSINFO 3 /* Contains copy of prpsinfo struct */
@@ -734,10 +734,10 @@ typedef struct {
#define NT_LWPSINFO 17 /* Contains copy of lwpinfo struct */
#define NT_PRFPXREG 20 /* Contains copy of fprxregset struct */
#define NT_SIGINFO \
0x53494749 /* Contains copy of siginfo_t,
0x53494749 /* Contains copy of siginfo_t, \
size might increase */
#define NT_FILE \
0x46494c45 /* Contains information about mapped
0x46494c45 /* Contains information about mapped \
files */
#define NT_PRXFPREG 0x46e62b7f /* Contains copy of user_fxsr_struct */
#define NT_PPC_VMX 0x100 /* PowerPC Altivec/VMX registers */
@@ -754,16 +754,16 @@ typedef struct {
#define NT_PPC_TM_CVSX 0x10b /* TM checkpointed VSX Registers */
#define NT_PPC_TM_SPR 0x10c /* TM Special Purpose Registers */
#define NT_PPC_TM_CTAR \
0x10d /* TM checkpointed Target Address
0x10d /* TM checkpointed Target Address \
Register */
#define NT_PPC_TM_CPPR \
0x10e /* TM checkpointed Program Priority
0x10e /* TM checkpointed Program Priority \
Register */
#define NT_PPC_TM_CDSCR \
0x10f /* TM checkpointed Data Stream Control
0x10f /* TM checkpointed Data Stream Control \
Register */
#define NT_PPC_PKEY \
0x110 /* Memory Protection Keys
0x110 /* Memory Protection Keys \
registers. */
#define NT_PPC_DEXCR 0x111 /* PowerPC DEXCR registers. */
#define NT_PPC_HASHKEYR 0x112 /* PowerPC HASHKEYR register. */
@@ -782,12 +782,12 @@ typedef struct {
#define NT_S390_SYSTEM_CALL 0x307 /* s390 system call restart data */
#define NT_S390_TDB 0x308 /* s390 transaction diagnostic block */
#define NT_S390_VXRS_LOW \
0x309 /* s390 vector registers 0-15
0x309 /* s390 vector registers 0-15 \
upper half. */
#define NT_S390_VXRS_HIGH 0x30a /* s390 vector registers 16-31. */
#define NT_S390_GS_CB 0x30b /* s390 guarded storage registers. */
#define NT_S390_GS_BC \
0x30c /* s390 guarded storage
0x30c /* s390 guarded storage \
broadcast control block. */
#define NT_S390_RI_CB 0x30d /* s390 runtime instrumentation. */
#define NT_S390_PV_CPU_DATA 0x30e /* s390 protvirt cpu dump data. */
@@ -797,22 +797,22 @@ typedef struct {
#define NT_ARM_HW_WATCH 0x403 /* ARM hardware watchpoint registers */
#define NT_ARM_SYSTEM_CALL 0x404 /* ARM system call number */
#define NT_ARM_SVE \
0x405 /* ARM Scalable Vector Extension
0x405 /* ARM Scalable Vector Extension \
registers */
#define NT_ARM_PAC_MASK \
0x406 /* ARM pointer authentication
0x406 /* ARM pointer authentication \
code masks. */
#define NT_ARM_PACA_KEYS \
0x407 /* ARM pointer authentication
0x407 /* ARM pointer authentication \
address keys. */
#define NT_ARM_PACG_KEYS \
0x408 /* ARM pointer authentication
0x408 /* ARM pointer authentication \
generic key. */
#define NT_ARM_TAGGED_ADDR_CTRL \
0x409 /* AArch64 tagged address
0x409 /* AArch64 tagged address \
control. */
#define NT_ARM_PAC_ENABLED_KEYS \
0x40a /* AArch64 pointer authentication
0x40a /* AArch64 pointer authentication \
enabled keys. */
#define NT_ARM_SSVE 0x40b /* ARM Streaming SVE registers. */
#define NT_ARM_ZA 0x40c /* ARM SME ZA registers. */
@@ -827,20 +827,20 @@ typedef struct {
#define NT_RISCV_CSR 0x900 /* RISC-V Control and Status Registers */
#define NT_RISCV_VECTOR 0x901 /* RISC-V vector registers */
#define NT_RISCV_TAGGED_ADDR_CTRL \
0x902 /* RISC-V tagged
0x902 /* RISC-V tagged \
address control */
#define NT_LOONGARCH_CPUCFG 0xa00 /* LoongArch CPU config registers. */
#define NT_LOONGARCH_CSR \
0xa01 /* LoongArch control and
0xa01 /* LoongArch control and \
status registers. */
#define NT_LOONGARCH_LSX \
0xa02 /* LoongArch Loongson SIMD
0xa02 /* LoongArch Loongson SIMD \
Extension registers. */
#define NT_LOONGARCH_LASX \
0xa03 /* LoongArch Loongson Advanced
0xa03 /* LoongArch Loongson Advanced \
SIMD Extension registers. */
#define NT_LOONGARCH_LBT \
0xa04 /* LoongArch Loongson Binary
0xa04 /* LoongArch Loongson Binary \
Translation registers. */
#define NT_LOONGARCH_HW_BREAK 0xa05 /* LoongArch hardware breakpoint registers */
#define NT_LOONGARCH_HW_WATCH 0xa06 /* LoongArch hardware watchpoint registers */
@@ -927,7 +927,7 @@ typedef struct {
#define DT_MOVESZ 0x6ffffdfb
#define DT_FEATURE_1 0x6ffffdfc /* Feature selection (DTF_*). */
#define DT_POSFLAG_1 \
0x6ffffdfd /* Flags for DT_* entries, effecting
0x6ffffdfd /* Flags for DT_* entries, effecting \
the following DT_* entry. */
#define DT_SYMINSZ 0x6ffffdfe /* Size of syminfo table (in bytes) */
#define DT_SYMINENT 0x6ffffdff /* Entry size of syminfo */
@@ -966,11 +966,11 @@ typedef struct {
/* These were chosen by Sun. */
#define DT_FLAGS_1 0x6ffffffb /* State flags, see DF_1_* below. */
#define DT_VERDEF \
0x6ffffffc /* Address of version definition
0x6ffffffc /* Address of version definition \
table */
#define DT_VERDEFNUM 0x6ffffffd /* Number of version definitions */
#define DT_VERNEED \
0x6ffffffe /* Address of table with needed
0x6ffffffe /* Address of table with needed \
versions */
#define DT_VERNEEDNUM 0x6fffffff /* Number of needed versions */
#define DT_VERSIONTAGIDX(tag) (DT_VERNEEDNUM - (tag)) /* Reverse order! */
@@ -1031,7 +1031,7 @@ typedef struct {
/* Flags in the DT_POSFLAG_1 entry effecting only the next DT_* entry. */
#define DF_P1_LAZYLOAD 0x00000001 /* Lazyload following object. */
#define DF_P1_GROUPPERM \
0x00000002 /* Symbols from next object are not
0x00000002 /* Symbols from next object are not \
generally available. */
/* Version definition sections. */
@@ -1066,7 +1066,7 @@ typedef struct {
/* Legal values for vd_flags (version information flags). */
#define VER_FLG_BASE 0x1 /* Version definition of file itself */
#define VER_FLG_WEAK \
0x2 /* Weak version identifier. Also
0x2 /* Weak version identifier. Also \
used by vna_flags below. */
/* Versym symbol index values. */
@@ -1187,7 +1187,7 @@ typedef struct {
/* Some more special a_type values describing the hardware. */
#define AT_PLATFORM 15 /* String identifying platform. */
#define AT_HWCAP \
16 /* Machine-dependent hints about
16 /* Machine-dependent hints about \
processor capabilities. */
/* This entry gives some information about the FPU initialization
@@ -1210,7 +1210,7 @@ typedef struct {
#define AT_RANDOM 25 /* Address of 16 random bytes. */
#define AT_HWCAP2 \
26 /* More machine-dependent hints about
26 /* More machine-dependent hints about \
processor capabilities. */
#define AT_RSEQ_FEATURE_SIZE 27 /* rseq supported feature size. */
@@ -1465,13 +1465,13 @@ typedef struct {
#define R_68K_TLS_IE16 35 /* 16 bit GOT offset for IE */
#define R_68K_TLS_IE8 36 /* 8 bit GOT offset for IE */
#define R_68K_TLS_LE32 \
37 /* 32 bit offset relative to
37 /* 32 bit offset relative to \
static TLS block */
#define R_68K_TLS_LE16 \
38 /* 16 bit offset relative to
38 /* 16 bit offset relative to \
static TLS block */
#define R_68K_TLS_LE8 \
39 /* 8 bit offset relative to
39 /* 8 bit offset relative to \
static TLS block */
#define R_68K_TLS_DTPMOD32 40 /* 32 bit module number */
#define R_68K_TLS_DTPREL32 41 /* 32 bit module-relative offset */
@@ -1497,47 +1497,47 @@ typedef struct {
#define R_386_32PLT 11
#define R_386_TLS_TPOFF 14 /* Offset in static TLS block */
#define R_386_TLS_IE \
15 /* Address of GOT entry for static TLS
15 /* Address of GOT entry for static TLS \
block offset */
#define R_386_TLS_GOTIE \
16 /* GOT entry for static TLS block
16 /* GOT entry for static TLS block \
offset */
#define R_386_TLS_LE \
17 /* Offset relative to static TLS
17 /* Offset relative to static TLS \
block */
#define R_386_TLS_GD \
18 /* Direct 32 bit for GNU version of
18 /* Direct 32 bit for GNU version of \
general dynamic thread local data */
#define R_386_TLS_LDM \
19 /* Direct 32 bit for GNU version of
local dynamic thread local data
19 /* Direct 32 bit for GNU version of \
local dynamic thread local data \
in LE code */
#define R_386_16 20
#define R_386_PC16 21
#define R_386_8 22
#define R_386_PC8 23
#define R_386_TLS_GD_32 \
24 /* Direct 32 bit for general dynamic
24 /* Direct 32 bit for general dynamic \
thread local data */
#define R_386_TLS_GD_PUSH 25 /* Tag for pushl in GD TLS code */
#define R_386_TLS_GD_CALL \
26 /* Relocation for call to
26 /* Relocation for call to \
__tls_get_addr() */
#define R_386_TLS_GD_POP 27 /* Tag for popl in GD TLS code */
#define R_386_TLS_LDM_32 \
28 /* Direct 32 bit for local dynamic
28 /* Direct 32 bit for local dynamic \
thread local data in LE code */
#define R_386_TLS_LDM_PUSH 29 /* Tag for pushl in LDM TLS code */
#define R_386_TLS_LDM_CALL \
30 /* Relocation for call to
30 /* Relocation for call to \
__tls_get_addr() in LDM code */
#define R_386_TLS_LDM_POP 31 /* Tag for popl in LDM TLS code */
#define R_386_TLS_LDO_32 32 /* Offset relative to TLS block */
#define R_386_TLS_IE_32 \
33 /* GOT entry for negated static TLS
33 /* GOT entry for negated static TLS \
block offset */
#define R_386_TLS_LE_32 \
34 /* Negated offset relative to static
34 /* Negated offset relative to static \
TLS block */
#define R_386_TLS_DTPMOD32 35 /* ID of module containing symbol */
#define R_386_TLS_DTPOFF32 36 /* Offset in TLS block */
@@ -1545,17 +1545,17 @@ typedef struct {
#define R_386_SIZE32 38 /* 32-bit symbol size */
#define R_386_TLS_GOTDESC 39 /* GOT offset for TLS descriptor. */
#define R_386_TLS_DESC_CALL \
40 /* Marker of call through TLS
descriptor for
40 /* Marker of call through TLS \
descriptor for \
relaxation. */
#define R_386_TLS_DESC \
41 /* TLS descriptor containing
pointer to code and to
argument, returning the TLS
41 /* TLS descriptor containing \
pointer to code and to \
argument, returning the TLS \
offset for the symbol. */
#define R_386_IRELATIVE 42 /* Adjust indirectly by program base */
#define R_386_GOT32X \
43 /* Load from 32 bit GOT entry,
43 /* Load from 32 bit GOT entry, \
relaxable. */
/* Keep this the last entry. */
#define R_386_NUM 44
@@ -1698,26 +1698,26 @@ typedef struct {
#define EF_MIPS_ABI2 32
#define EF_MIPS_ABI_ON32 64
#define EF_MIPS_OPTIONS_FIRST \
0x00000080 /* Process the .MIPS.options
0x00000080 /* Process the .MIPS.options \
section first by ld. */
#define EF_MIPS_32BITMODE \
0x00000100 /* Indicates code compiled for
a 64-bit machine in 32-bit
mode (regs are 32-bits
0x00000100 /* Indicates code compiled for \
a 64-bit machine in 32-bit \
mode (regs are 32-bits \
wide). */
#define EF_MIPS_FP64 512 /* Uses FP64 (12 callee-saved). */
#define EF_MIPS_NAN2008 1024 /* Uses IEEE 754-2008 NaN encoding. */
#define EF_MIPS_ARCH_ASE \
0x0f000000 /* Architectural Extensions
0x0f000000 /* Architectural Extensions \
used by this file. */
#define EF_MIPS_ARCH_ASE_MDMX \
0x08000000 /* Use MDMX multimedia
0x08000000 /* Use MDMX multimedia \
extensions. */
#define EF_MIPS_ARCH_ASE_M16 \
0x04000000 /* Use MIPS-16 ISA
0x04000000 /* Use MIPS-16 ISA \
extensions. */
#define EF_MIPS_ARCH_ASE_MICROMIPS \
0x02000000 /* Use MICROMIPS ISA
0x02000000 /* Use MICROMIPS ISA \
extensions. */
#define EF_MIPS_ARCH 0xf0000000 /* MIPS architecture level. */
@@ -1735,11 +1735,11 @@ typedef struct {
#define EF_MIPS_ARCH_32R6 0x90000000 /* MIPS32r6 code. */
#define EF_MIPS_ARCH_64R6 0xa0000000 /* MIPS64r6 code. */
#define EF_MIPS_ABI \
0x0000F000 /* The ABI of the file. Also
0x0000F000 /* The ABI of the file. Also \
see EF_MIPS_ABI2 above. */
#define EF_MIPS_ABI_O32 0x00001000 /* The original o32 abi. */
#define EF_MIPS_ABI_O64 \
0x00002000 /* O32 extended to work on
0x00002000 /* O32 extended to work on \
64 bit architectures. */
#define EF_MIPS_ABI_EABI32 0x00003000 /* EABI in 32 bit mode. */
#define EF_MIPS_ABI_EABI64 0x00004000 /* EABI in 64 bit mode. */
@@ -2083,27 +2083,27 @@ typedef struct {
#define DT_MIPS_RLD_MAP 0x70000016 /* Address of run time loader map. */
#define DT_MIPS_DELTA_CLASS 0x70000017 /* Delta C++ class definition. */
#define DT_MIPS_DELTA_CLASS_NO \
0x70000018 /* Number of entries in
0x70000018 /* Number of entries in \
DT_MIPS_DELTA_CLASS. */
#define DT_MIPS_DELTA_INSTANCE 0x70000019 /* Delta C++ class instances. */
#define DT_MIPS_DELTA_INSTANCE_NO \
0x7000001a /* Number of entries in
0x7000001a /* Number of entries in \
DT_MIPS_DELTA_INSTANCE. */
#define DT_MIPS_DELTA_RELOC 0x7000001b /* Delta relocations. */
#define DT_MIPS_DELTA_RELOC_NO \
0x7000001c /* Number of entries in
0x7000001c /* Number of entries in \
DT_MIPS_DELTA_RELOC. */
#define DT_MIPS_DELTA_SYM \
0x7000001d /* Delta symbols that Delta
0x7000001d /* Delta symbols that Delta \
relocations refer to. */
#define DT_MIPS_DELTA_SYM_NO \
0x7000001e /* Number of entries in
0x7000001e /* Number of entries in \
DT_MIPS_DELTA_SYM. */
#define DT_MIPS_DELTA_CLASSSYM \
0x70000020 /* Delta symbols that hold the
0x70000020 /* Delta symbols that hold the \
class declaration. */
#define DT_MIPS_DELTA_CLASSSYM_NO \
0x70000021 /* Number of entries in
0x70000021 /* Number of entries in \
DT_MIPS_DELTA_CLASSSYM. */
#define DT_MIPS_CXX_FLAGS 0x70000022 /* Flags indicating for C++ flavor. */
#define DT_MIPS_PIXIE_INIT 0x70000023
@@ -2117,10 +2117,10 @@ typedef struct {
#define DT_MIPS_DYNSTR_ALIGN 0x7000002b
#define DT_MIPS_INTERFACE_SIZE 0x7000002c /* Size of the .interface section. */
#define DT_MIPS_RLD_TEXT_RESOLVE_ADDR \
0x7000002d /* Address of rld_text_rsolve
0x7000002d /* Address of rld_text_rsolve \
function stored in GOT. */
#define DT_MIPS_PERF_SUFFIX \
0x7000002e /* Default suffix of dso to be added
0x7000002e /* Default suffix of dso to be added \
by rld on dlopen() calls. */
#define DT_MIPS_COMPACT_SIZE 0x7000002f /* (O32)Size of compact rel section. */
#define DT_MIPS_GP_VALUE 0x70000030 /* GP value for aux GOTs. */
@@ -2293,7 +2293,7 @@ enum {
#define EF_PARISC_LSB 0x00040000 /* Program expects little endian. */
#define EF_PARISC_WIDE 0x00080000 /* Program expects wide mode. */
#define EF_PARISC_NO_KABP \
0x00100000 /* No kernel assisted branch
0x00100000 /* No kernel assisted branch \
prediction. */
#define EF_PARISC_LAZYSWAP 0x00400000 /* Allow lazy swapping. */
#define EF_PARISC_ARCH 0x0000ffff /* Architecture version. */
@@ -2307,7 +2307,7 @@ enum {
/* Additional section indices. */
#define SHN_PARISC_ANSI_COMMON \
0xff00 /* Section for tentatively declared
0xff00 /* Section for tentatively declared \
symbols in ANSI C. */
#define SHN_PARISC_HUGE_COMMON 0xff01 /* Common blocks in huge model. */
@@ -2555,7 +2555,7 @@ enum {
/* Cygnus local bits below */
#define EF_PPC_RELOCATABLE 0x00010000 /* PowerPC -mrelocatable flag*/
#define EF_PPC_RELOCATABLE_LIB \
0x00008000 /* PowerPC -mrelocatable-lib
0x00008000 /* PowerPC -mrelocatable-lib \
flag */
/* PowerPC relocations defined by the ABIs */
@@ -2877,12 +2877,12 @@ enum {
/* ARM-specific values for sh_flags */
#define SHF_ARM_ENTRYSECT 0x10000000 /* Section contains an entry point */
#define SHF_ARM_COMDEF \
0x80000000 /* Section may be multiply defined
0x80000000 /* Section may be multiply defined \
in the input to a link step. */
/* ARM-specific program header flags */
#define PF_ARM_SB \
0x10000000 /* Segment contains the location
0x10000000 /* Segment contains the location \
addressed by the static base. */
#define PF_ARM_PI 0x20000000 /* Position-independent segment. */
#define PF_ARM_ABS 0x40000000 /* Absolute segment. */
@@ -3038,7 +3038,7 @@ enum {
#define R_ARM_NONE 0 /* No reloc */
#define R_ARM_PC24 \
1 /* Deprecated PC relative 26
1 /* Deprecated PC relative 26 \
bit branch. */
#define R_ARM_ABS32 2 /* Direct 32 bit */
#define R_ARM_REL32 3 /* PC relative 32 bit */
@@ -3050,7 +3050,7 @@ enum {
#define R_ARM_SBREL32 9
#define R_ARM_THM_PC22 10 /* PC relative 24 bit (Thumb32 BL). */
#define R_ARM_THM_PC8 \
11 /* PC relative & 0x3FC
11 /* PC relative & 0x3FC \
(Thumb16 LDR, ADD, ADR). */
#define R_ARM_AMP_VCALL9 12
#define R_ARM_SWI24 13 /* Obsolete static relocation. */
@@ -3071,7 +3071,7 @@ enum {
#define R_ARM_PLT32 27 /* Deprecated, 32 bit PLT address. */
#define R_ARM_CALL 28 /* PC relative 24 bit (BL, BLX). */
#define R_ARM_JUMP24 \
29 /* PC relative 24 bit
29 /* PC relative 24 bit \
(B, BL<cond>). */
#define R_ARM_THM_JUMP24 30 /* PC relative 24 bit (Thumb32 B.W). */
#define R_ARM_BASE_ABS 31 /* Adjust by program base. */
@@ -3092,25 +3092,25 @@ enum {
#define R_ARM_MOVT_PREL 46 /* PC relative (MOVT). */
#define R_ARM_THM_MOVW_ABS_NC 47 /* Direct 16 bit (Thumb32 MOVW). */
#define R_ARM_THM_MOVT_ABS \
48 /* Direct high 16 bit
48 /* Direct high 16 bit \
(Thumb32 MOVT). */
#define R_ARM_THM_MOVW_PREL_NC \
49 /* PC relative 16 bit
49 /* PC relative 16 bit \
(Thumb32 MOVW). */
#define R_ARM_THM_MOVT_PREL \
50 /* PC relative high 16 bit
50 /* PC relative high 16 bit \
(Thumb32 MOVT). */
#define R_ARM_THM_JUMP19 \
51 /* PC relative 20 bit
51 /* PC relative 20 bit \
(Thumb32 B<cond>.W). */
#define R_ARM_THM_JUMP6 \
52 /* PC relative X & 0x7E
52 /* PC relative X & 0x7E \
(Thumb16 CBZ, CBNZ). */
#define R_ARM_THM_ALU_PREL_11_0 \
53 /* PC relative 12 bit
53 /* PC relative 12 bit \
(Thumb32 ADR.W). */
#define R_ARM_THM_PC12 \
54 /* PC relative 12 bit
54 /* PC relative 12 bit \
(Thumb32 LDR{D,SB,H,SH}). */
#define R_ARM_ABS32_NOI 55 /* Direct 32-bit. */
#define R_ARM_REL32_NOI 56 /* PC relative 32-bit. */
@@ -3122,13 +3122,13 @@ enum {
#define R_ARM_LDR_PC_G1 62 /* PC relative (LDR,STR,LDRB,STRB). */
#define R_ARM_LDR_PC_G2 63 /* PC relative (LDR,STR,LDRB,STRB). */
#define R_ARM_LDRS_PC_G0 \
64 /* PC relative (STR{D,H},
64 /* PC relative (STR{D,H}, \
LDR{D,SB,H,SH}). */
#define R_ARM_LDRS_PC_G1 \
65 /* PC relative (STR{D,H},
65 /* PC relative (STR{D,H}, \
LDR{D,SB,H,SH}). */
#define R_ARM_LDRS_PC_G2 \
66 /* PC relative (STR{D,H},
66 /* PC relative (STR{D,H}, \
LDR{D,SB,H,SH}). */
#define R_ARM_LDC_PC_G0 67 /* PC relative (LDC, STC). */
#define R_ARM_LDC_PC_G1 68 /* PC relative (LDC, STC). */
@@ -3139,43 +3139,43 @@ enum {
#define R_ARM_ALU_SB_G1 73 /* Program base relative (ADD,SUB). */
#define R_ARM_ALU_SB_G2 74 /* Program base relative (ADD,SUB). */
#define R_ARM_LDR_SB_G0 \
75 /* Program base relative (LDR,
75 /* Program base relative (LDR, \
STR, LDRB, STRB). */
#define R_ARM_LDR_SB_G1 \
76 /* Program base relative
76 /* Program base relative \
(LDR, STR, LDRB, STRB). */
#define R_ARM_LDR_SB_G2 \
77 /* Program base relative
77 /* Program base relative \
(LDR, STR, LDRB, STRB). */
#define R_ARM_LDRS_SB_G0 \
78 /* Program base relative
78 /* Program base relative \
(LDR, STR, LDRB, STRB). */
#define R_ARM_LDRS_SB_G1 \
79 /* Program base relative
79 /* Program base relative \
(LDR, STR, LDRB, STRB). */
#define R_ARM_LDRS_SB_G2 \
80 /* Program base relative
80 /* Program base relative \
(LDR, STR, LDRB, STRB). */
#define R_ARM_LDC_SB_G0 81 /* Program base relative (LDC,STC). */
#define R_ARM_LDC_SB_G1 82 /* Program base relative (LDC,STC). */
#define R_ARM_LDC_SB_G2 83 /* Program base relative (LDC,STC). */
#define R_ARM_MOVW_BREL_NC \
84 /* Program base relative 16
84 /* Program base relative 16 \
bit (MOVW). */
#define R_ARM_MOVT_BREL \
85 /* Program base relative high
85 /* Program base relative high \
16 bit (MOVT). */
#define R_ARM_MOVW_BREL \
86 /* Program base relative 16
86 /* Program base relative 16 \
bit (MOVW). */
#define R_ARM_THM_MOVW_BREL_NC \
87 /* Program base relative 16
87 /* Program base relative 16 \
bit (Thumb32 MOVW). */
#define R_ARM_THM_MOVT_BREL \
88 /* Program base relative high
88 /* Program base relative high \
16 bit (Thumb32 MOVT). */
#define R_ARM_THM_MOVW_BREL \
89 /* Program base relative 16
89 /* Program base relative 16 \
bit (Thumb32 MOVW). */
#define R_ARM_TLS_GOTDESC 90
#define R_ARM_TLS_CALL 91
@@ -3185,48 +3185,48 @@ enum {
#define R_ARM_GOT_ABS 95 /* GOT entry. */
#define R_ARM_GOT_PREL 96 /* PC relative GOT entry. */
#define R_ARM_GOT_BREL12 \
97 /* GOT entry relative to GOT
97 /* GOT entry relative to GOT \
origin (LDR). */
#define R_ARM_GOTOFF12 \
98 /* 12 bit, GOT entry relative
98 /* 12 bit, GOT entry relative \
to GOT origin (LDR, STR). */
#define R_ARM_GOTRELAX 99
#define R_ARM_GNU_VTENTRY 100
#define R_ARM_GNU_VTINHERIT 101
#define R_ARM_THM_PC11 102 /* PC relative & 0xFFE (Thumb16 B). */
#define R_ARM_THM_PC9 \
103 /* PC relative & 0x1FE
103 /* PC relative & 0x1FE \
(Thumb16 B/B<cond>). */
#define R_ARM_TLS_GD32 \
104 /* PC-rel 32 bit for global dynamic
104 /* PC-rel 32 bit for global dynamic \
thread local data */
#define R_ARM_TLS_LDM32 \
105 /* PC-rel 32 bit for local dynamic
105 /* PC-rel 32 bit for local dynamic \
thread local data */
#define R_ARM_TLS_LDO32 \
106 /* 32 bit offset relative to TLS
106 /* 32 bit offset relative to TLS \
block */
#define R_ARM_TLS_IE32 \
107 /* PC-rel 32 bit for GOT entry of
107 /* PC-rel 32 bit for GOT entry of \
static TLS block offset */
#define R_ARM_TLS_LE32 \
108 /* 32 bit offset relative to static
108 /* 32 bit offset relative to static \
TLS block */
#define R_ARM_TLS_LDO12 \
109 /* 12 bit relative to TLS
109 /* 12 bit relative to TLS \
block (LDR, STR). */
#define R_ARM_TLS_LE12 \
110 /* 12 bit relative to static
110 /* 12 bit relative to static \
TLS block (LDR, STR). */
#define R_ARM_TLS_IE12GP \
111 /* 12 bit GOT entry relative
111 /* 12 bit GOT entry relative \
to GOT origin (LDR). */
#define R_ARM_ME_TOO 128 /* Obsolete. */
#define R_ARM_THM_TLS_DESCSEQ 129
#define R_ARM_THM_TLS_DESCSEQ16 129
#define R_ARM_THM_TLS_DESCSEQ32 130
#define R_ARM_THM_GOT_BREL12 \
131 /* GOT entry relative to GOT
131 /* GOT entry relative to GOT \
origin, 12 bit (Thumb32 LDR). */
#define R_ARM_IRELATIVE 160
#define R_ARM_RXPC25 249
@@ -3540,63 +3540,63 @@ enum {
#define R_390_PLTOFF64 36 /* 16 bit offset from GOT to PLT. */
#define R_390_TLS_LOAD 37 /* Tag for load insn in TLS code. */
#define R_390_TLS_GDCALL \
38 /* Tag for function call in general
38 /* Tag for function call in general \
dynamic TLS code. */
#define R_390_TLS_LDCALL \
39 /* Tag for function call in local
39 /* Tag for function call in local \
dynamic TLS code. */
#define R_390_TLS_GD32 \
40 /* Direct 32 bit for general dynamic
40 /* Direct 32 bit for general dynamic \
thread local data. */
#define R_390_TLS_GD64 \
41 /* Direct 64 bit for general dynamic
41 /* Direct 64 bit for general dynamic \
thread local data. */
#define R_390_TLS_GOTIE12 \
42 /* 12 bit GOT offset for static TLS
42 /* 12 bit GOT offset for static TLS \
block offset. */
#define R_390_TLS_GOTIE32 \
43 /* 32 bit GOT offset for static TLS
43 /* 32 bit GOT offset for static TLS \
block offset. */
#define R_390_TLS_GOTIE64 \
44 /* 64 bit GOT offset for static TLS
44 /* 64 bit GOT offset for static TLS \
block offset. */
#define R_390_TLS_LDM32 \
45 /* Direct 32 bit for local dynamic
45 /* Direct 32 bit for local dynamic \
thread local data in LE code. */
#define R_390_TLS_LDM64 \
46 /* Direct 64 bit for local dynamic
46 /* Direct 64 bit for local dynamic \
thread local data in LE code. */
#define R_390_TLS_IE32 \
47 /* 32 bit address of GOT entry for
47 /* 32 bit address of GOT entry for \
negated static TLS block offset. */
#define R_390_TLS_IE64 \
48 /* 64 bit address of GOT entry for
48 /* 64 bit address of GOT entry for \
negated static TLS block offset. */
#define R_390_TLS_IEENT \
49 /* 32 bit rel. offset to GOT entry for
49 /* 32 bit rel. offset to GOT entry for \
negated static TLS block offset. */
#define R_390_TLS_LE32 \
50 /* 32 bit negated offset relative to
50 /* 32 bit negated offset relative to \
static TLS block. */
#define R_390_TLS_LE64 \
51 /* 64 bit negated offset relative to
51 /* 64 bit negated offset relative to \
static TLS block. */
#define R_390_TLS_LDO32 \
52 /* 32 bit offset relative to TLS
52 /* 32 bit offset relative to TLS \
block. */
#define R_390_TLS_LDO64 \
53 /* 64 bit offset relative to TLS
53 /* 64 bit offset relative to TLS \
block. */
#define R_390_TLS_DTPMOD 54 /* ID of module containing symbol. */
#define R_390_TLS_DTPOFF 55 /* Offset in TLS block. */
#define R_390_TLS_TPOFF \
56 /* Negated offset in static TLS
56 /* Negated offset in static TLS \
block. */
#define R_390_20 57 /* Direct 20 bit. */
#define R_390_GOT20 58 /* 20 bit GOT offset. */
#define R_390_GOTPLT20 59 /* 20 bit offset to jump slot. */
#define R_390_TLS_GOTIE20 \
60 /* 20 bit GOT offset for static TLS
60 /* 20 bit GOT offset for static TLS \
block offset. */
#define R_390_IRELATIVE 61 /* STT_GNU_IFUNC relocation. */
/* Keep this the last entry. */
@@ -3637,7 +3637,7 @@ enum {
#define R_X86_64_JUMP_SLOT 7 /* Create PLT entry */
#define R_X86_64_RELATIVE 8 /* Adjust by program base */
#define R_X86_64_GOTPCREL \
9 /* 32 bit signed PC relative
9 /* 32 bit signed PC relative \
offset to GOT */
#define R_X86_64_32 10 /* Direct 32 bit zero extended */
#define R_X86_64_32S 11 /* Direct 32 bit sign extended */
@@ -3649,35 +3649,35 @@ enum {
#define R_X86_64_DTPOFF64 17 /* Offset in module's TLS block */
#define R_X86_64_TPOFF64 18 /* Offset in initial TLS block */
#define R_X86_64_TLSGD \
19 /* 32 bit signed PC relative offset
19 /* 32 bit signed PC relative offset \
to two GOT entries for GD symbol */
#define R_X86_64_TLSLD \
20 /* 32 bit signed PC relative offset
20 /* 32 bit signed PC relative offset \
to two GOT entries for LD symbol */
#define R_X86_64_DTPOFF32 21 /* Offset in TLS block */
#define R_X86_64_GOTTPOFF \
22 /* 32 bit signed PC relative offset
22 /* 32 bit signed PC relative offset \
to GOT entry for IE symbol */
#define R_X86_64_TPOFF32 23 /* Offset in initial TLS block */
#define R_X86_64_PC64 24 /* PC relative 64 bit */
#define R_X86_64_GOTOFF64 25 /* 64 bit offset to GOT */
#define R_X86_64_GOTPC32 \
26 /* 32 bit signed pc relative
26 /* 32 bit signed pc relative \
offset to GOT */
#define R_X86_64_GOT64 27 /* 64-bit GOT entry offset */
#define R_X86_64_GOTPCREL64 \
28 /* 64-bit PC relative offset
28 /* 64-bit PC relative offset \
to GOT entry */
#define R_X86_64_GOTPC64 29 /* 64-bit PC relative offset to GOT */
#define R_X86_64_GOTPLT64 30 /* like GOT64, says PLT entry needed */
#define R_X86_64_PLTOFF64 \
31 /* 64-bit GOT relative offset
31 /* 64-bit GOT relative offset \
to PLT entry */
#define R_X86_64_SIZE32 32 /* Size of symbol plus 32-bit addend */
#define R_X86_64_SIZE64 33 /* Size of symbol plus 64-bit addend */
#define R_X86_64_GOTPC32_TLSDESC 34 /* GOT offset for TLS descriptor. */
#define R_X86_64_TLSDESC_CALL \
35 /* Marker for call through TLS
35 /* Marker for call through TLS \
descriptor. */
#define R_X86_64_TLSDESC 36 /* TLS descriptor. */
#define R_X86_64_IRELATIVE 37 /* Adjust indirectly by program base */
@@ -3685,12 +3685,12 @@ enum {
/* 39 Reserved was R_X86_64_PC32_BND */
/* 40 Reserved was R_X86_64_PLT32_BND */
#define R_X86_64_GOTPCRELX \
41 /* Load from 32 bit signed pc relative
offset to GOT entry without REX
41 /* Load from 32 bit signed pc relative \
offset to GOT entry without REX \
prefix, relaxable. */
#define R_X86_64_REX_GOTPCRELX \
42 /* Load from 32 bit signed pc relative
offset to GOT entry with REX prefix,
42 /* Load from 32 bit signed pc relative \
offset to GOT entry with REX prefix, \
relaxable. */
#define R_X86_64_NUM 43
@@ -3732,22 +3732,22 @@ enum {
#define R_MN10300_TLS_LD 25 /* 32-bit offset for local dynamic. */
#define R_MN10300_TLS_LDO 26 /* Module-relative offset. */
#define R_MN10300_TLS_GOTIE \
27 /* GOT offset for static TLS block
27 /* GOT offset for static TLS block \
offset. */
#define R_MN10300_TLS_IE \
28 /* GOT address for static TLS block
28 /* GOT address for static TLS block \
offset. */
#define R_MN10300_TLS_LE \
29 /* Offset relative to static TLS
29 /* Offset relative to static TLS \
block. */
#define R_MN10300_TLS_DTPMOD 30 /* ID of module containing symbol. */
#define R_MN10300_TLS_DTPOFF 31 /* Offset in module TLS block. */
#define R_MN10300_TLS_TPOFF 32 /* Offset in static TLS block. */
#define R_MN10300_SYM_DIFF \
33 /* Adjustment for next reloc as needed
33 /* Adjustment for next reloc as needed \
by linker relaxation. */
#define R_MN10300_ALIGN \
34 /* Alignment requirement for linker
34 /* Alignment requirement for linker \
relaxation. */
#define R_MN10300_NUM 35
@@ -3789,26 +3789,26 @@ enum {
#define R_M32R_GOTOFF 54 /* 24 bit offset to GOT */
#define R_M32R_GOTPC24 55 /* 24 bit PC relative offset to GOT */
#define R_M32R_GOT16_HI_ULO \
56 /* High 16 bit GOT entry with unsigned
56 /* High 16 bit GOT entry with unsigned \
low */
#define R_M32R_GOT16_HI_SLO \
57 /* High 16 bit GOT entry with signed
57 /* High 16 bit GOT entry with signed \
low */
#define R_M32R_GOT16_LO 58 /* Low 16 bit GOT entry */
#define R_M32R_GOTPC_HI_ULO \
59 /* High 16 bit PC relative offset to
59 /* High 16 bit PC relative offset to \
GOT with unsigned low */
#define R_M32R_GOTPC_HI_SLO \
60 /* High 16 bit PC relative offset to
60 /* High 16 bit PC relative offset to \
GOT with signed low */
#define R_M32R_GOTPC_LO \
61 /* Low 16 bit PC relative offset to
61 /* Low 16 bit PC relative offset to \
GOT */
#define R_M32R_GOTOFF_HI_ULO \
62 /* High 16 bit offset to GOT
62 /* High 16 bit offset to GOT \
with unsigned low */
#define R_M32R_GOTOFF_HI_SLO \
63 /* High 16 bit offset to GOT
63 /* High 16 bit offset to GOT \
with signed low */
#define R_M32R_GOTOFF_LO 64 /* Low 16 bit offset to GOT */
#define R_M32R_NUM 256 /* Keep this the last entry. */
@@ -3871,7 +3871,7 @@ enum {
#define R_NIOS2_CJMP 19 /* Conditional branch. */
#define R_NIOS2_CALLR 20 /* Indirect call through register. */
#define R_NIOS2_ALIGN \
21 /* Alignment requirement for
21 /* Alignment requirement for \
linker relaxation. */
#define R_NIOS2_GOT16 22 /* 16 bit GOT entry. */
#define R_NIOS2_CALL16 23 /* 16 bit GOT entry for function. */
@@ -4195,7 +4195,7 @@ enum {
/* RISC-V specific values for the st_other field. */
#define STO_RISCV_VARIANT_CC \
0x80 /* Function uses variant calling
0x80 /* Function uses variant calling \
convention */
/* RISC-V specific values for the sh_type field. */

2
kernel/mm/liballoc.c
View File

@@ -45,7 +45,7 @@ int liballoc_free (void* ptr, int pages) {
/** Durand's Ridiculously Amazing Super Duper Memory functions. */
//#define DEBUG
// #define DEBUG
#define LIBALLOC_MAGIC 0xc001c0de
#define MAXCOMPLETE 5

4
kernel/mm/pmm.c
View File

@@ -38,8 +38,8 @@ void pmm_init (void) {
struct pmm_region* pmm_region = &pmm.regions[region];
/*
* We need to calculate sizes for the pmm region and the bitmap. The bitmap MUSTN'T include it's
* own region within the bit range.
* We need to calculate sizes for the pmm region and the bitmap. The bitmap MUSTN'T include
* it's own region within the bit range.
* */
size_t size = align_down (entry->length, PAGE_SIZE);