Remove Doxygen-style comments, change formatting to wrap comments
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@@ -9,7 +9,7 @@
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#define TSS 0x80
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#define TSS_PRESENT 0x89
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/// Set a GDT entry
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/* Set a GDT entry */
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static void amd64_gdt_set (volatile struct gdt_entry* ent, uint32_t base, uint32_t limit,
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uint8_t acc, uint8_t gran) {
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ent->baselow = (base & 0xFFFF);
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@@ -20,7 +20,7 @@ static void amd64_gdt_set (volatile struct gdt_entry* ent, uint32_t base, uint32
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ent->access = acc;
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}
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/// Initialize GDT and TSS structures for a given CPU
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/* Initialize GDT and TSS structures for a given CPU */
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static void amd64_gdt_init (struct cpu* cpu) {
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volatile struct tss* tss = &cpu->tss;
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volatile struct gdt_extended* gdt = &cpu->gdt;
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@@ -51,11 +51,13 @@ static void amd64_gdt_init (struct cpu* cpu) {
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gdt->tsshigh.access = 0;
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gdt->tsshigh.gran = 0;
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/* Load GDTR */
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struct gdt_ptr gdtr;
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gdtr.limit = sizeof (*gdt) - 1;
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gdtr.base = (uint64_t)gdt;
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__asm__ volatile ("lgdt %0" ::"m"(gdtr) : "memory");
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/* Reload CS */
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__asm__ volatile ("pushq %[kcode]\n"
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"lea 1f(%%rip), %%rax\n"
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"pushq %%rax\n"
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@@ -72,11 +74,10 @@ static void amd64_gdt_init (struct cpu* cpu) {
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__asm__ volatile ("ltr %0" ::"r"((uint16_t)GDT_TSS));
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}
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/**
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* @brief Initialize essentials (GDT, TSS, IDT) for a given CPU
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/*
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* Initialize essentials (GDT, TSS, IDT) for a given CPU
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*
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* @param load_idt
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* Tell whether the IDT needs to be loaded. It only has to be loaded once on
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* load_idt - Tell whether the IDT needs to be loaded. It only has to be loaded once on
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* the BSP
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*/
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void amd64_init (struct cpu* cpu, bool load_idt) {
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