Remove Doxygen-style comments, change formatting to wrap comments

kernel/amd64/apic.c

@@ -16,49 +16,49 @@
 #define IOAPICS_MAX                 24
 #define INTERRUPT_SRC_OVERRIDES_MAX 24
 
-/// ID of Local APIC
+/* ID of Local APIC */
 #define LAPIC_ID 0x20
-/// End of interrupt register
+/* End of interrupt register */
 #define LAPIC_EOI 0xB0
-/// Spurious interrupt vector register
+/* Spurious interrupt vector register */
 #define LAPIC_SIVR 0xF0
-/// Interrupt command register
+/* Interrupt command register */
 #define LAPIC_ICR 0x300
-/// LVT timer register
+/* LVT timer register */
 #define LAPIC_LVTTR 0x320
-/// Timer initial count register
+/* Timer initial count register */
 #define LAPIC_TIMICT 0x380
-/// Timer current count register
+/* Timer current count register */
 #define LAPIC_TIMCCT 0x390
-/// Divide config register
+/* Divide config register */
 #define LAPIC_DCR 0x3E0
 
-/// Table of IOAPICS
+/* Table of IOAPICS */
 static struct acpi_madt_ioapic apics[IOAPICS_MAX];
+/* Table of interrupt source overrides */
 /* clang-format off */
-/// Table of interrupt source overrides
 static struct acpi_madt_interrupt_source_override intr_src_overrides[INTERRUPT_SRC_OVERRIDES_MAX];
 /* clang-format on */
-/// Count of actual IOAPIC entries
+/* Count of actual IOAPIC entries */
 static size_t ioapic_entries = 0;
-/// Count of actual interrupt source overrides
+/* Count of actual interrupt source overrides */
 static size_t intr_src_override_entries = 0;
-/// Local APIC MMIO base address. It comes from MSR_APIC_BASE
+/* Local APIC MMIO base address. It comes from MSR_APIC_BASE */
 static uintptr_t lapic_mmio_base = 0;
 
-/// Read IOAPIC
+/* Read IOAPIC */
 static uint32_t amd64_ioapic_read (uintptr_t vaddr, uint32_t reg) {
   *(volatile uint32_t*)vaddr = reg;
   return *(volatile uint32_t*)(vaddr + 0x10);
 }
 
-/// Write IOAPIC
+/* Write IOAPIC */
 static void amd64_ioapic_write (uintptr_t vaddr, uint32_t reg, uint32_t value) {
   *(volatile uint32_t*)vaddr = reg;
   *(volatile uint32_t*)(vaddr + 0x10) = value;
 }
 
-/// Find an IOAPIC corresposting to provided IRQ
+/* Find an IOAPIC corresposting to provided IRQ */
 static struct acpi_madt_ioapic* amd64_ioapic_find (uint8_t irq) {
   struct acpi_madt_ioapic* apic = NULL;
   struct limine_hhdm_response* hhdm = limine_hhdm_request.response;
@@ -75,21 +75,14 @@ static struct acpi_madt_ioapic* amd64_ioapic_find (uint8_t irq) {
   return NULL;
 }
 
-/**
- * @brief Route IRQ to an IDT entry of a given Local APIC.
+/*
+ * Route IRQ to an IDT entry of a given Local APIC.
  *
- * @param vec
- *  Interrupt vector number, which will be delivered to the CPU
- *
- * @param irq
- *  Legacy IRQ number to be routed. Can be changed by an interrupt source override
+ * vec - Interrupt vector number, which will be delivered to the CPU.
+ * irq -Legacy IRQ number to be routed. Can be changed by an interrupt source override
  *  into a different GSI.
- *
- * @param flags
- *  IOAPIC redirection flags.
- *
- * @param lapic_id
- *  Local APIC that will receive the interrupt.
+ * flags - IOAPIC redirection flags.
+ * lapic_id - Local APIC that will receive the interrupt.
  */
 void amd64_ioapic_route_irq (uint8_t vec, uint8_t irq, uint64_t flags, uint64_t lapic_id) {
   struct acpi_madt_ioapic* apic = NULL;
@@ -132,7 +125,7 @@ void amd64_ioapic_route_irq (uint8_t vec, uint8_t irq, uint64_t flags, uint64_t
                       (uint32_t)(calc_flags >> 32));
 }
 
-/// Mask a given IRQ
+/* Mask a given IRQ */
 void amd64_ioapic_mask (uint8_t irq) {
   struct acpi_madt_ioapic* apic;
   struct limine_hhdm_response* hhdm = limine_hhdm_request.response;
@@ -149,7 +142,7 @@ void amd64_ioapic_mask (uint8_t irq) {
                       value | (1 << 16));
 }
 
-/// Unmask a given IRQ
+/* Unmask a given IRQ */
 void amd64_ioapic_unmask (uint8_t irq) {
   struct acpi_madt_ioapic* apic;
   struct limine_hhdm_response* hhdm = limine_hhdm_request.response;
@@ -166,7 +159,7 @@ void amd64_ioapic_unmask (uint8_t irq) {
                       value & ~(1 << 16));
 }
 
-/// Find and initialize the IOAPIC
+/* Find and initialize the IOAPIC */
 void amd64_ioapic_init (void) {
   struct limine_hhdm_response* hhdm = limine_hhdm_request.response;
 
@@ -204,35 +197,32 @@ void amd64_ioapic_init (void) {
   }
 }
 
-/// Get MMIO base of Local APIC
+/* Get MMIO base of Local APIC */
 static uintptr_t amd64_lapic_base (void) { return lapic_mmio_base; }
 
-/// Write Local APIC
+/* Write Local APIC */
 static void amd64_lapic_write (uint32_t reg, uint32_t value) {
   *(volatile uint32_t*)(amd64_lapic_base () + reg) = value;
 }
 
-/// Read Local APIC
+/* Read Local APIC */
 static uint32_t amd64_lapic_read (uint32_t reg) {
   return *(volatile uint32_t*)(amd64_lapic_base () + reg);
 }
 
-/// Get ID of Local APIC
+/* Get ID of Local APIC */
 uint32_t amd64_lapic_id (void) { return amd64_lapic_read (LAPIC_ID) >> 24; }
 
-/// Send End of interrupt command to Local APIC
+/* Send End of interrupt command to Local APIC */
 void amd64_lapic_eoi (void) { amd64_lapic_write (LAPIC_EOI, 0); }
 
-/// Set initial counter value in Local APIC timer
+/* Set initial counter value in Local APIC timer */
 void amd64_lapic_tick (uint32_t tick) { amd64_lapic_write (LAPIC_TIMICT, tick); }
 
-/**
- * @brief Calibrate Local APIC to send interrupts in a set interval.
+/*
+ * Calibrate Local APIC to send interrupts in a set interval.
  *
- * @param us
- *  Period length in microseconds
- *
- * @return amount of ticsk in a given period
+ * us - Period length in microseconds
  */
 static uint32_t amd64_lapic_calibrate (uint32_t us) {
   amd64_lapic_write (LAPIC_DCR, 0x0B);
@@ -248,12 +238,10 @@ static uint32_t amd64_lapic_calibrate (uint32_t us) {
   return ticks;
 }
 
-/**
- * @brief Starts a Local APIC, configures LVT timer to
- * send interrupts at \ref SCHED_PREEMPT_TIMER.
+/*
+ * Starts a Local APIC, configures LVT timer to send interrupts at SCHED_PREEMPT_TIMER.
  *
- * @param ticks
- *  Initial tick count
+ * ticks - Initial tick count
  */
 static void amd64_lapic_start (uint32_t ticks) {
   amd64_lapic_write (LAPIC_DCR, 0x0B);
@@ -263,9 +251,9 @@ static void amd64_lapic_start (uint32_t ticks) {
   amd64_lapic_write (LAPIC_TIMICT, ticks);
 }
 
-/**
- * @brief Initialize Local APIC, configure to send timer interrupts
- * at a given period. See \ref amd64_lapic_calibrate and \ref amd64_lapic_start.
+/*
+ * Initialize Local APIC, configure to send timer interrupts at a given period. See
+ * amd64_lapic_calibrate and amd64_lapic_start.
  */
 uint64_t amd64_lapic_init (uint32_t us) {
   struct limine_hhdm_response* hhdm = limine_hhdm_request.response;
@@ -287,14 +275,11 @@ uint64_t amd64_lapic_init (uint32_t us) {
   return ticks;
 }
 
-/**
- * @brief Send an IPI to a given Local APIC. This till invoke an IDT stub located at vec.
+/*
+ * Send an IPI to a given Local APIC. This till invoke an IDT stub located at vec.
  *
- * @param lapic_id
- *  Target Local APIC
- *
- * @param vec
- *  Interrupt vector/IDT stub, which will be invoked by the IPI.
+ * lapic_id - Target Local APIC
+ * vec - Interrupt vector/IDT stub, which will be invoked by the IPI.
  */
 void amd64_lapic_ipi (uint8_t lapic_id, uint8_t vec) {
   amd64_lapic_write (LAPIC_ICR + 0x10, (lapic_id << 24));