organize device drivers into subdirectories

kernel/device/pci/.gitignore

@@ -0,0 +1 @@
+*.o

kernel/device/pci/pci.c

@@ -0,0 +1,328 @@
+#include <amd64/io.h>
+#include <device/pci/pci.h>
+#include <device/pci/pci_ide.h>
+#include <device/pci/pci_info.h>
+#include <device/pci/pci_xhci.h>
+#include <libk/lengthof.h>
+#include <libk/std.h>
+#include <libk/string.h>
+#include <limine/requests.h>
+#include <sync/spin_lock.h>
+#include <sys/debug.h>
+#include <sys/smp.h>
+
+static const struct pci_driver_info pci_driver_infos[] = {
+    {.class = 0x01, .subclass = 0x01, .init = &pci_ide_init},
+    {.class = 0x0C, .subclass = 0x03, .init = &pci_xhci_init},
+};
+
+static spin_lock_t pci_lock = SPIN_LOCK_INIT;
+
+uint32_t pci_read32 (uint8_t bus, uint8_t slot, uint8_t func, uint8_t offset) {
+  uint64_t fpci;
+
+  uint32_t addr = (uint32_t)((uint32_t)bus << 16) | ((uint32_t)slot << 11) | ((uint32_t)func << 8) |
+      (offset & 0xFC) | ((uint32_t)0x80000000);
+
+  spin_lock (&pci_lock, &fpci);
+
+  outl (PCI_CONFIG_ADDR, addr);
+  uint32_t r = inl (PCI_CONFIG_DATA);
+
+  spin_unlock (&pci_lock, fpci);
+
+  return r;
+}
+
+void pci_write32 (uint8_t bus, uint8_t slot, uint8_t func, uint8_t offset, uint32_t value) {
+  uint64_t fpci;
+
+  uint32_t addr = (uint32_t)((uint32_t)bus << 16) | ((uint32_t)slot << 11) | ((uint32_t)func << 8) |
+      (offset & 0xFC) | ((uint32_t)0x80000000);
+
+  spin_lock (&pci_lock, &fpci);
+
+  outl (PCI_CONFIG_ADDR, addr);
+  outl (PCI_CONFIG_DATA, value);
+
+  spin_unlock (&pci_lock, fpci);
+}
+
+uint16_t pci_read16 (uint8_t bus, uint8_t slot, uint8_t func, uint8_t offset) {
+  uint64_t fpci;
+
+  uint32_t addr = (uint32_t)((uint32_t)bus << 16) | ((uint32_t)slot << 11) | ((uint32_t)func << 8) |
+      (offset & 0xFC) | ((uint32_t)0x80000000);
+
+  spin_lock (&pci_lock, &fpci);
+
+  outl (PCI_CONFIG_ADDR, addr);
+  uint16_t r = inw (PCI_CONFIG_DATA + (offset & 2));
+
+  spin_unlock (&pci_lock, fpci);
+
+  return r;
+}
+
+void pci_write16 (uint8_t bus, uint8_t slot, uint8_t func, uint8_t offset, uint16_t value) {
+  uint64_t fpci;
+
+  uint32_t addr = (uint32_t)((uint32_t)bus << 16) | ((uint32_t)slot << 11) | ((uint32_t)func << 8) |
+      (offset & 0xFC) | ((uint32_t)0x80000000);
+
+  spin_lock (&pci_lock, &fpci);
+
+  outl (PCI_CONFIG_ADDR, addr);
+  outw (PCI_CONFIG_DATA + (offset & 2), value);
+
+  spin_unlock (&pci_lock, fpci);
+}
+
+uint8_t pci_read8 (uint8_t bus, uint8_t slot, uint8_t func, uint8_t offset) {
+  uint64_t fpci;
+
+  uint32_t addr = (uint32_t)((uint32_t)bus << 16) | ((uint32_t)slot << 11) | ((uint32_t)func << 8) |
+      (offset & 0xFC) | ((uint32_t)0x80000000);
+
+  spin_lock (&pci_lock, &fpci);
+
+  outl (PCI_CONFIG_ADDR, addr);
+  uint8_t r = inb (PCI_CONFIG_DATA + (offset & 3));
+
+  spin_unlock (&pci_lock, fpci);
+
+  return r;
+}
+
+void pci_write8 (uint8_t bus, uint8_t slot, uint8_t func, uint8_t offset, uint8_t value) {
+  uint64_t fpci;
+
+  uint32_t addr = (uint32_t)((uint32_t)bus << 16) | ((uint32_t)slot << 11) | ((uint32_t)func << 8) |
+      (offset & 0xFC) | ((uint32_t)0x80000000);
+
+  spin_lock (&pci_lock, &fpci);
+
+  outl (PCI_CONFIG_ADDR, addr);
+  outb (PCI_CONFIG_DATA + (offset & 3), value);
+
+  spin_unlock (&pci_lock, fpci);
+}
+
+uint8_t pci_find_cap (uint8_t bus, uint8_t slot, uint8_t func, uint8_t cap_id) {
+  uint16_t status = pci_read16 (bus, slot, func, PCI_STATUS);
+
+  if (!(status & (1 << 4)))
+    return 0;
+
+  uint8_t cap = pci_read8 (bus, slot, func, PCI_CAPABILITY);
+
+  while (cap != 0) {
+    uint8_t id = pci_read8 (bus, slot, func, cap);
+
+    if (id == cap_id)
+      return cap;
+
+    cap = pci_read8 (bus, slot, func, cap + 1);
+  }
+
+  return 0;
+}
+
+uint64_t pci_get_bar_size (uint8_t bus, uint8_t slot, uint8_t func, uint8_t offset) {
+  uint32_t bar = pci_read32 (bus, slot, func, offset);
+
+  pci_write32 (bus, slot, func, offset, 0xFFFFFFFF);
+
+  uint32_t mask = pci_read32 (bus, slot, func, offset);
+
+  pci_write32 (bus, slot, func, offset, bar);
+
+  if (mask == 0)
+    return 0;
+
+  uint64_t full_mask;
+  if ((bar & PCI_BAR_MEM32) || (bar & PCI_BAR_MEM64)) {
+    full_mask = mask & ~0xF;
+
+    if ((bar & PCI_BAR_MEM64)) {
+      uint32_t bar_hi = pci_read32 (bus, slot, func, offset + 4);
+      pci_write32 (bus, slot, func, offset + 4, 0xFFFFFFFF);
+      uint32_t mask_hi = pci_read32 (bus, slot, func, offset + 4);
+      pci_write32 (bus, slot, func, offset + 4, bar_hi);
+
+      full_mask |= ((uint64_t)mask_hi << 32);
+    }
+  } else {
+    full_mask = mask & ~0x3;
+    full_mask |= 0xFFFFFFFF00000000ULL;
+  }
+
+  return (~full_mask) + 1;
+}
+
+bool pci_msi_init (uint8_t bus, uint8_t slot, uint8_t func, uint8_t vec, uint32_t lapic_id) {
+  struct limine_hhdm_response* hhdm = limine_hhdm_request.response;
+
+  uint8_t cap = pci_find_cap (bus, slot, func, PCI_CAP_MSI);
+
+  if (cap == 0) {
+    DEBUG ("Device does not support MSI\n");
+    return false;
+  }
+
+  uint16_t msg_ctrl = pci_read16 (bus, slot, func, cap + 2);
+
+  uintptr_t lapic_phys = thiscpu->lapic_mmio_base - (uintptr_t)hhdm->offset;
+
+  uint32_t msi_addr = (uint32_t)lapic_phys | (lapic_id << 12);
+
+  uint32_t msi_data = (uint32_t)vec & 0xFF;
+
+  pci_write32 (bus, slot, func, cap + 4, msi_addr);
+
+  /* 32 or 64 bit */
+  if (msg_ctrl & (1 << 7)) {
+    /* 64 */
+    pci_write32 (bus, slot, func, cap + 12, msi_data);
+  } else {
+    pci_write32 (bus, slot, func, cap + 8, msi_data);
+  }
+
+  pci_write16 (bus, slot, func, cap + 2, msg_ctrl | 0x0001);
+
+  DEBUG ("MSI enabled (lapic %u)\n", lapic_id);
+
+  return true;
+}
+
+static void pci_check_bus (struct proc* proc, struct reschedule_ctx* rctx, uint8_t bus,
+                           pci_cb_func_t cb);
+
+static void pci_check_func (struct proc* proc, struct reschedule_ctx* rctx, uint8_t bus,
+                            uint8_t slot, uint8_t func, pci_cb_func_t cb) {
+  uint32_t reg0 = pci_read32 (bus, slot, func, PCI_VENDOR_ID);
+  uint16_t vendor = (uint16_t)(reg0 & 0xFFFF);
+
+  if (vendor == 0xFFFF)
+    return;
+
+  uint32_t reg8 = pci_read32 (bus, slot, func, PCI_REVISION_ID);
+
+  struct pci_info pci_info = {
+      .bus = bus,
+      .slot = slot,
+      .func = func,
+      .vendor = vendor,
+      .device = ((uint16_t)(reg0 >> 16)),
+      .class = ((uint8_t)(reg8 >> 24)),
+      .subclass = ((uint8_t)(reg8 >> 16)),
+  };
+
+  cb (proc, rctx, pci_info);
+
+  /* PCI 2 PCI bridge */
+  if (pci_info.class == 0x06 && pci_info.subclass == 0x04) {
+    uint32_t reg18 = pci_read32 (bus, slot, func, 0x18);
+    uint8_t secondary = (uint8_t)(reg18 >> 8);
+    pci_check_bus (proc, rctx, secondary, cb);
+  }
+}
+
+static void pci_check_device (struct proc* proc, struct reschedule_ctx* rctx, uint8_t bus,
+                              uint8_t slot, pci_cb_func_t cb) {
+  uint32_t reg0 = pci_read32 (bus, slot, 0, PCI_VENDOR_ID);
+
+  if ((uint16_t)(reg0 & 0xFFFF) == 0xFFFF)
+    return;
+
+  pci_check_func (proc, rctx, bus, slot, 0, cb);
+
+  /* multifunc device */
+  uint32_t reg0xc = pci_read32 (bus, slot, 0, PCI_CACHELINE);
+  if ((reg0xc >> 16) & 0x80) {
+    for (uint8_t func = 1; func < 8; func++)
+      pci_check_func (proc, rctx, bus, slot, func, cb);
+  }
+}
+
+static void pci_check_bus (struct proc* proc, struct reschedule_ctx* rctx, uint8_t bus,
+                           pci_cb_func_t cb) {
+  for (uint8_t slot = 0; slot < 32; slot++)
+    pci_check_device (proc, rctx, bus, slot, cb);
+}
+
+static void pci_enumerate (struct proc* proc, struct reschedule_ctx* rctx, pci_cb_func_t cb) {
+  uint32_t reg0xc = pci_read32 (0, 0, 0, PCI_CACHELINE);
+  bool is_multictrl = (reg0xc >> 16) & 0x80;
+
+  if (!is_multictrl)
+    pci_check_bus (proc, rctx, 0, cb);
+  else {
+    for (uint8_t func = 0; func < 8; func++) {
+      if ((pci_read32 (0, 0, func, PCI_VENDOR_ID) & 0xFFFF) != 0xFFFF)
+        pci_check_bus (proc, rctx, func, cb);
+    }
+  }
+}
+
+static void pci_string_identifiers (uint16_t vendor_id, uint16_t device_id, uint8_t class_id,
+                                    uint8_t subclass_id, const char** vname, const char** dname,
+                                    const char** cname) {
+  *vname = "Unknown vendor";
+  *dname = "Unknown device";
+  *cname = "Unknown class";
+
+  for (size_t i = 0; pci_vendors[i].name; i++) {
+    if (pci_vendors[i].id == vendor_id) {
+      *vname = pci_vendors[i].name;
+      break;
+    }
+  }
+
+  for (size_t i = 0; pci_device_names[i].name; i++) {
+    if (pci_device_names[i].vendor_id == vendor_id && pci_device_names[i].device_id == device_id) {
+      *dname = pci_device_names[i].name;
+      break;
+    }
+  }
+
+  for (size_t i = 0; pci_classes[i].name; i++) {
+    if (pci_classes[i].class == class_id && pci_classes[i].subclass == subclass_id) {
+      *cname = pci_classes[i].name;
+      break;
+    }
+  }
+}
+
+static void pci_discovery_cb (struct proc* proc, struct reschedule_ctx* rctx,
+                              struct pci_info pci_info) {
+  const char *vname, *dname, *cname;
+  pci_string_identifiers (pci_info.vendor, pci_info.device, pci_info.class, pci_info.subclass,
+                          &vname, &dname, &cname);
+
+  DEBUG ("PCI DEVICE: %04x:%04x %02x:%02x at %03d:%03d:%03d / %s; %s; %s\n", pci_info.vendor,
+         pci_info.device, pci_info.class, pci_info.subclass, pci_info.bus, pci_info.slot,
+         pci_info.func, vname, dname, cname);
+
+  uint8_t cap = pci_find_cap (pci_info.bus, pci_info.slot, pci_info.func, PCI_CAP_MSI);
+
+  if (cap) {
+    DEBUG ("Device supports MSI!\n");
+  }
+
+  for (size_t driver = 0; driver < lengthof (pci_driver_infos); driver++) {
+    if (pci_driver_infos[driver].class == pci_info.class &&
+        pci_driver_infos[driver].subclass == pci_info.subclass) {
+      if (!pci_driver_infos[driver].init (proc, rctx, pci_info)) {
+        DEBUG ("Init failed. Skipping this device!\n");
+      }
+    }
+  }
+}
+
+void pci_init (void) {
+  struct reschedule_ctx rctx;
+  memset (&rctx, 0, sizeof (rctx));
+
+  pci_enumerate (thiscpu->kproc, &rctx, &pci_discovery_cb);
+}

kernel/device/pci/pci.h

@@ -0,0 +1,93 @@
+#ifndef _KERNEL_DEVICE_PCI_H
+#define _KERNEL_DEVICE_PCI_H
+
+#include <device/pci/pci_info.h>
+#include <libk/std.h>
+#include <proc/proc.h>
+#include <proc/reschedule.h>
+
+#define PCI_CONFIG_ADDR 0xCF8
+#define PCI_CONFIG_DATA 0xCFC
+
+#define PCI_VENDOR_ID      0x00
+#define PCI_DEVICE_ID      0x02
+#define PCI_COMMAND        0x04
+#define PCI_STATUS         0x06
+#define PCI_REVISION_ID    0x08
+#define PCI_PROG_IF        0x09
+#define PCI_SUBCLASS       0x0A
+#define PCI_CLASS          0x0B
+#define PCI_CACHELINE      0x0C
+#define PCI_LATENCY        0x0D
+#define PCI_HEADER_TYPE    0x0E
+#define PCI_BIST           0x0F
+#define PCI_BAR0           0x10
+#define PCI_BAR1           0x14
+#define PCI_BAR2           0x18
+#define PCI_BAR3           0x1C
+#define PCI_BAR4           0x20
+#define PCI_BAR5           0x24
+#define PCI_CAPABILITY     0x34
+#define PCI_INTERRUPT_LINE 0x3C
+#define PCI_INTERRUPT_PIN  0x3D
+
+#define PCI_BAR_IO       0x01
+#define PCI_BAR_MEM32    0x02
+#define PCI_BAR_MEM64    0x04
+#define PCI_BAR_PREFETCH 0x08
+
+#define PCI_CAP_MSI 0x05
+
+struct pci_vendor {
+  uint16_t id;
+  const char* name;
+};
+
+struct pci_device_id {
+  uint16_t vendor_id;
+  uint16_t device_id;
+  const char* name;
+};
+
+struct pci_class {
+  uint8_t class;
+  uint8_t subclass;
+  const char* name;
+};
+
+struct pci_driver_info {
+  uint8_t class;
+  uint8_t subclass;
+  bool (*init) (struct proc* proc, struct reschedule_ctx* rctx, struct pci_info pci_info);
+};
+
+typedef void (*pci_cb_func_t) (struct proc* proc, struct reschedule_ctx* rctx,
+                               struct pci_info pci_info);
+
+void pci_init (void);
+
+uint32_t pci_read32 (uint8_t bus, uint8_t slot, uint8_t func, uint8_t offset);
+
+void pci_write32 (uint8_t bus, uint8_t slot, uint8_t func, uint8_t offset, uint32_t value);
+
+uint16_t pci_read16 (uint8_t bus, uint8_t slot, uint8_t func, uint8_t offset);
+
+void pci_write16 (uint8_t bus, uint8_t slot, uint8_t func, uint8_t offset, uint16_t value);
+
+uint8_t pci_read8 (uint8_t bus, uint8_t slot, uint8_t func, uint8_t offset);
+
+void pci_write8 (uint8_t bus, uint8_t slot, uint8_t func, uint8_t offset, uint8_t value);
+
+uint8_t pci_find_cap (uint8_t bus, uint8_t slot, uint8_t func, uint8_t cap_id);
+
+bool pci_msi_init (uint8_t bus, uint8_t slot, uint8_t func, uint8_t vec, uint32_t lapic_id);
+
+uint64_t pci_get_bar_size (uint8_t bus, uint8_t slot, uint8_t func, uint8_t bar_offset);
+
+extern const struct pci_vendor pci_vendors[];
+
+extern const struct pci_device_id pci_device_names[];
+
+extern const struct pci_class pci_classes[];
+
+#endif // _KERNEL_DEVICE_PCI_H

kernel/device/pci/pci_ide.c

@@ -0,0 +1,161 @@
+#include <amd64/apic.h>
+#include <amd64/intr_defs.h>
+#include <amd64/io.h>
+#include <device/device.h>
+#include <device/pci/pci.h>
+#include <device/pci/pci_info.h>
+#include <device/storage/idedrv.h>
+#include <device/storage/partitions.h>
+#include <devices.h>
+#include <libk/fieldsizeof.h>
+#include <libk/lengthof.h>
+#include <libk/printf.h>
+#include <libk/std.h>
+#include <proc/proc.h>
+#include <proc/reschedule.h>
+#include <sys/debug.h>
+
+static int ide_counter = 0;
+
+static const char* progif_msg[] = {
+    [0x00] = "ISA Compatibility mode-only controller",
+    [0x05] = "PCI native mode-only controller",
+    [0x0A] =
+        "ISA Compatibility mode controller, supports both channels switched to PCI native mode",
+    [0x0F] =
+        "PCI native mode controller, supports both channels switched to ISA compatibility mode",
+    [0x80] = "ISA Compatibility mode-only controller, supports bus mastering",
+    [0x85] = "PCI native mode-only controller, supports bus mastering",
+    [0x8A] =
+        "ISA Compatibility mode controller, supports both channels switched to PCI native mode, supports bus mastering",
+    [0x8F] =
+        "PCI native mode controller, supports both channels switched to ISA compatibility mode, supports bus mastering",
+};
+
+static void ide_make_device (struct proc* proc, struct reschedule_ctx* rctx,
+                             struct ide_probe probe) {
+  DEBUG ("Found IDE drive: io=%x ctrl=%x no=%u sector=%zu count=%zu\n", probe.io, probe.ctrl,
+         probe.devno, probe.sector_size, probe.sector_count);
+
+  char device_key[fieldsizeof (struct device, key)];
+  snprintf (device_key, sizeof (device_key), "ide%d", ide_counter++);
+
+  device_op_func_t ops[] = {
+      [XDRV_GET_SIZE] = &idedrv_get_size,
+      [XDRV_GET_SECTOR_SIZE] = &idedrv_get_sector_size,
+      [XDRV_GET_DEVICE_TYPE] = &idedrv_get_device_type,
+      [XDRV_READ] = &idedrv_read,
+      [XDRV_WRITE] = &idedrv_write,
+  };
+
+  struct idedrv_init init = {
+      .lba48 = ((probe.flags & IDE_PROBE_LBA48) != 0),
+      .sector_count = probe.sector_count,
+      .sector_size = probe.sector_size,
+      .io = probe.io,
+      .ctrl = probe.ctrl,
+      .devno = probe.devno,
+      .irq = probe.irq,
+      .irqs_support = probe.irqs_support,
+  };
+  struct device* ide = device_create (DEVICE_TYPE_DRIVE, device_key, ops, lengthof (ops),
+                                      &idedrv_init, &idedrv_fini, &init, proc, rctx);
+  device_probe_partitions (proc, rctx, ide);
+}
+
+bool pci_ide_init (struct proc* proc, struct reschedule_ctx* rctx, struct pci_info pci_info) {
+  uint16_t pci_cmd = pci_read16 (pci_info.bus, pci_info.slot, pci_info.func, PCI_COMMAND);
+
+  uint16_t new_cmd = (pci_cmd | (1 << 0) | (1 << 2)) & ~(1 << 10);
+
+  if (pci_cmd != new_cmd) {
+    pci_write16 (pci_info.bus, pci_info.slot, pci_info.func, PCI_COMMAND, new_cmd);
+  }
+
+  struct ide_probe probe;
+
+  uint8_t progif = pci_read8 (pci_info.bus, pci_info.slot, pci_info.func, PCI_PROG_IF);
+  DEBUG ("progif: %s\n", progif_msg[progif]);
+
+  uint16_t pcmd, pctrl, scmd, sctrl;
+
+  if ((progif & 0x01)) {
+    uint32_t bar0 = pci_read32 (pci_info.bus, pci_info.slot, pci_info.func, PCI_BAR0);
+    uint32_t bar1 = pci_read32 (pci_info.bus, pci_info.slot, pci_info.func, PCI_BAR1);
+
+    if (!(bar0 & PCI_BAR_IO) || !(bar1 & PCI_BAR_IO)) {
+      DEBUG ("Non IO BARs not supported\n");
+      return false;
+    }
+
+    pcmd = (uint16_t)(bar0 & 0xFFFC);
+    pctrl = (uint16_t)(bar1 & 0xFFFC);
+
+    if (pctrl)
+      pctrl += 2;
+  } else {
+    pcmd = 0x1F0;
+    pctrl = 0x3F6;
+  }
+
+  if ((progif & 0x04)) {
+    uint32_t bar2 = pci_read32 (pci_info.bus, pci_info.slot, pci_info.func, PCI_BAR2);
+    uint32_t bar3 = pci_read32 (pci_info.bus, pci_info.slot, pci_info.func, PCI_BAR3);
+
+    if (!(bar2 & PCI_BAR_IO) || !(bar3 & PCI_BAR_IO)) {
+      DEBUG ("Non IO BARs not supported\n");
+      return false;
+    }
+
+    scmd = (uint16_t)(bar2 & 0xFFFC);
+    sctrl = (uint16_t)(bar3 & 0xFFFC);
+
+    if (sctrl)
+      sctrl += 2;
+  } else {
+    scmd = 0x170;
+    sctrl = 0x376;
+  }
+
+  bool irqs_support = false;
+
+  if ((progif & 0x05)) {
+    irqs_support = false;
+  } else {
+    irqs_support = true;
+
+    if (!pci_msi_init (pci_info.bus, pci_info.slot, pci_info.func, INTR_IDE_DRIVE_PRIM,
+                       thiscpu->lapic_id)) {
+      ioapic_route_irq (INTR_IDE_DRIVE_PRIM, 14, 0, thiscpu->lapic_id);
+      ioapic_route_irq (INTR_IDE_DRIVE_SCND, 15, 0, thiscpu->lapic_id);
+      DEBUG ("Fallback to IOAPIC interrupt routing\n");
+    }
+  }
+
+  DEBUG ("pcmd=%x, pctrl=%x\n", pcmd, pctrl);
+  DEBUG ("scmd=%x, sctrl=%x\n", scmd, sctrl);
+  DEBUG ("IRQ support=%d\n", irqs_support);
+
+  uint16_t channels[2][3] = {{pcmd, pctrl, INTR_IDE_DRIVE_PRIM},
+                             {scmd, sctrl, INTR_IDE_DRIVE_SCND}};
+
+  for (size_t i = 0; i < lengthof (channels); i++) {
+    uint16_t cmd = channels[i][0];
+    uint16_t ctrl = channels[i][1];
+    uint8_t irq = channels[i][2];
+
+    for (size_t dev = 0; dev < 2; dev++) {
+      ide_probe (cmd, ctrl, dev, &probe);
+
+      probe.ctrl = ctrl;
+      probe.io = cmd;
+      probe.irq = irq;
+      probe.irqs_support = irqs_support;
+
+      if ((probe.flags & IDE_PROBE_AVAIL))
+        ide_make_device (proc, rctx, probe);
+    }
+  }
+
+  return true;
+}

kernel/device/pci/pci_ide.h

@@ -0,0 +1,11 @@
+#ifndef _KERNEL_DEVICE_PCI_IDE_H
+#define _KERNEL_DEVICE_PCI_IDE_H
+
+#include <device/pci/pci_info.h>
+#include <libk/std.h>
+#include <proc/proc.h>
+#include <proc/reschedule.h>
+
+bool pci_ide_init (struct proc* proc, struct reschedule_ctx* rctx, struct pci_info pci_info);
+
+#endif // _KERNEL_DEVICE_PCI_IDE_H

kernel/device/pci/pci_info.h

@@ -0,0 +1,16 @@
+#ifndef _KERNEL_DEVICE_PCI_INFO_H
+#define _KERNEL_DEVICE_PCI_INFO_H
+
+#include <libk/std.h>
+
+struct pci_info {
+  uint8_t bus;
+  uint8_t slot;
+  uint8_t func;
+  uint16_t vendor;
+  uint16_t device;
+  uint8_t class;
+  uint8_t subclass;
+};
+
+#endif // _KERNEL_DEVICE_PCI_INFO_H

kernel/device/pci/pci_xhci.c

@@ -0,0 +1,107 @@
+#include <amd64/apic.h>
+#include <amd64/intr_defs.h>
+#include <device/def_device_op.h>
+#include <device/device.h>
+#include <device/pci/pci.h>
+#include <device/pci/pci_info.h>
+#include <device/pci/pci_xhci.h>
+#include <device/usb/xhci.h>
+#include <devices.h>
+#include <libk/align.h>
+#include <libk/lengthof.h>
+#include <libk/printf.h>
+#include <libk/std.h>
+#include <limine/requests.h>
+#include <proc/proc.h>
+#include <proc/reschedule.h>
+#include <sys/debug.h>
+#include <sys/mm.h>
+
+static bool xhci_init_done = false;
+
+bool pci_xhci_init (struct proc* proc, struct reschedule_ctx* rctx, struct pci_info pci_info) {
+  struct limine_hhdm_response* hhdm = limine_hhdm_request.response;
+
+  uint8_t progif = pci_read8 (pci_info.bus, pci_info.slot, pci_info.func, PCI_PROG_IF);
+
+  /* not an XHCI controller */
+  if (progif != 0x30) {
+    return true;
+  }
+
+  if (xhci_init_done) {
+    DEBUG ("Cannot initialize more XHCI controllers\n");
+    return false;
+  }
+
+  uint16_t pci_cmd = pci_read16 (pci_info.bus, pci_info.slot, pci_info.func, PCI_COMMAND);
+
+  uint16_t new_cmd = (pci_cmd | (1 << 1) | (1 << 2)) & ~(1 << 10);
+
+  if (pci_cmd != new_cmd) {
+    pci_write16 (pci_info.bus, pci_info.slot, pci_info.func, PCI_COMMAND, new_cmd);
+  }
+
+  uintptr_t xhci_phys = 0;
+  size_t map_pages = 0;
+
+  uint32_t bar0 = pci_read32 (pci_info.bus, pci_info.slot, pci_info.func, PCI_BAR0);
+  map_pages = pci_get_bar_size (pci_info.bus, pci_info.slot, pci_info.func, PCI_BAR0);
+  map_pages = div_align_up (map_pages, PAGE_SIZE);
+
+  if ((bar0 & 0x6) == 0x4) {
+    uint32_t bar1 = pci_read32 (pci_info.bus, pci_info.slot, pci_info.func, PCI_BAR1);
+    xhci_phys = ((uint64_t)bar1 << 32) | (bar0 & ~0xF);
+    DEBUG ("XHCI phys base addr=%p (64 bit)\n", xhci_phys);
+  } else {
+    xhci_phys = (bar0 & ~0xF);
+    DEBUG ("XHCI phys base addr=%p (32 bit)\n", xhci_phys);
+  }
+
+  if (xhci_phys == 0) {
+    DEBUG ("WARNING xhci_phys is NULL!\n");
+    return false;
+  }
+
+  uintptr_t xhci_base = xhci_phys + (uintptr_t)hhdm->offset;
+
+  DEBUG ("BAR size = %zu pages\n", map_pages);
+
+  for (size_t page = 0; page < map_pages; page++) {
+    mm_map_kernel_page (xhci_phys + page * PAGE_SIZE, xhci_base + page * PAGE_SIZE,
+                        MM_PG_RW | MM_PG_PRESENT | MM_PG_NOCACHE);
+  }
+
+  bool irqs_support = false;
+
+  if (!pci_msi_init (pci_info.bus, pci_info.slot, pci_info.func, INTR_XHCI, thiscpu->lapic_id)) {
+    uint8_t intr_line = pci_read8 (pci_info.bus, pci_info.slot, pci_info.func, PCI_INTERRUPT_LINE);
+    uint8_t intr_pin = pci_read8 (pci_info.bus, pci_info.slot, pci_info.func, PCI_INTERRUPT_PIN);
+
+    if (intr_pin != 0) {
+      irqs_support = true;
+      ioapic_route_irq (INTR_XHCI, intr_line, 0, thiscpu->lapic_id);
+    }
+  } else {
+    irqs_support = true;
+  }
+
+  DEBUG ("IRQ support=%d\n", irqs_support);
+
+  struct xhci_init init = {
+      .xhci_mmio_base = xhci_base,
+      .irqs_support = irqs_support,
+      .irq = INTR_XHCI,
+  };
+
+  device_op_func_t ops[] = {
+      [XUSBCTRL_POLL_DRIVER] = &xhci_poll_driver,
+  };
+
+  device_create (DEVICE_TYPE_USB_CTRL, "xhci", ops, lengthof (ops), &xhci_init, &xhci_fini, &init,
+                 proc, rctx);
+
+  xhci_init_done = true;
+
+  return true;
+}

kernel/device/pci/pci_xhci.h

@@ -0,0 +1,11 @@
+#ifndef _KERNEL_DEVICE_PCI_XHCI_H
+#define _KERNEL_DEVICE_PCI_XHCI_H
+
+#include <device/pci/pci_info.h>
+#include <libk/std.h>
+#include <proc/proc.h>
+#include <proc/reschedule.h>
+
+bool pci_xhci_init (struct proc* proc, struct reschedule_ctx* rctx, struct pci_info pci_info);
+
+#endif // _KERNEL_DEVICE_PCI_XHCI_H

kernel/device/pci/src.mk

@@ -0,0 +1,9 @@
+c += device/pci/pci.c \
+		 device/pci/pci_defs.c \
+		 device/pci/pci_ide.c \
+		 device/pci/pci_xhci.c
+
+o += device/pci/pci.o \
+		 device/pci/pci_defs.o \
+		 device/pci/pci_ide.o \
+		 device/pci/pci_xhci.o