Read USB mass storage sector count and sector size!
This commit is contained in:
@@ -19,293 +19,12 @@
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#include <sys/spin_lock.h>
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#include <sys/stall.h>
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/* REF:
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* https://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/extensible-host-controler-interface-usb-xhci.pdf
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*/
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/* clang-format off */
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/* capability registers */
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#define XHCI_CAPLENGTH 0x00
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#define XHCI_RSVD 0x01
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#define XHCI_HCIVERSION 0x02
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#define XHCI_HCSPARAMS1 0x04
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#define XHCI_HCSPARAMS2 0x08
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#define XHCI_HCSPARAMS3 0x0C
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#define XHCI_HCCPARAMS1 0x10
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#define XHCI_DBOFF 0x14
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#define XHCI_RTSOFF 0x18
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#define XHCI_HCCPARAMS2 0x1C
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/* operational registers */
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#define XHCI_USBCMD 0x00
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#define XHCI_USBSTS 0x04
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#define XHCI_PAGESIZE 0x08
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#define XHCI_DNCTRL 0x14
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#define XHCI_CRCR 0x18
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#define XHCI_DCBAAP 0x30
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#define XHCI_CONFIG 0x38
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/* port registers */
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#define XHCI_PORTSC 0x00
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#define XHCI_PORTPMSC 0x04
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#define XHCI_PORTLI 0x08
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/* runtime registers */
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#define XHCI_MFINDEX 0x00
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/* + IRQ sets (0x20) */
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#define XHCI_IMAN 0x00
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#define XHCI_IMOD 0x04
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#define XHCI_ERSTSZ 0x08
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#define XHCI_ERSTBA 0x10
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#define XHCI_ERDP 0x18
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/* HCCPARAMS1 */
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#define XHCI_HCCPARAMS1_AC64 0
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#define XHCI_HCCPARAMS1_BNC 1
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#define XHCI_HCCPARAMS1_CSZ 2
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#define XHCI_HCCPARAMS1_PPC 3
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#define XHCI_HCCPARAMS1_PIND 4
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#define XHCI_HCCPARAMS1_LHRC 5
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#define XHCI_HCCPARAMS1_LTC 6
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#define XHCI_HCCPARAMS1_NSS 7
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#define XHCI_HCCPARAMS1_PAE 8
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#define XHCI_HCCPARAMS1_SPC 9
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#define XHCI_HCCPARAMS1_SEC 10
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#define XHCI_HCCPARAMS1_CFC 11
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#define XHCI_HCCPARAMS1_MAX_PSA_SIZE 12
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#define XHCI_HCCPARAMS1_XECP 16
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/* XHCI extended capabilities */
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#define XHCI_XECP_CAP_ID 0
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#define XHCI_XECP_NEXT_PTR 8
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/* USB legacy support capability */
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#define XHCI_USBLEGSUP_CAP_ID 0
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#define XHCI_USBLEGSUP_NEXT_PTR 8
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#define XHCI_USBLEGSUP_BIOS_SEMA 16
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#define XHCI_USBLEGSUP_OS_SEMA 24
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/* Supported protocol capability */
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#define XHCI_SUPPROTO_DW0_CAP_ID 0
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#define XHCI_SUPPROTO_DW0_NEXT_PTR 8
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#define XHCI_SUPPROTO_DW0_MINOR_REV 16
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#define XHCI_SUPPROTO_DW0_MAJOR_REV 24
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#define XHCI_SUPPROTO_DW1_NAME_STRING 0
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#define XHCI_SUPPROTO_DW2_PORT_OFF 0
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#define XHCI_SUPPROTO_DW2_PORT_COUNT 8
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#define XHCI_SUPPROTO_DW2_PROT_DEF 16
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#define XHCI_SUPPROTO_DW2_PSIC 28
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#define XHCI_SUPPROTO_DW3_SLOT_TYPE 0
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/* HCSPARAMS1 */
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#define XHCI_HCSPARAMS1_MAX_DEV_SLOTS 0
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#define XHCI_HCSPARAMS1_MAX_INTRS 8
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#define XHCI_HCSPARAMS1_MAX_PORTS 24
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/* HCSPARAMS2 */
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#define XHCI_HCSPARAMS2_IST 0
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#define XHCI_HCSPARAMS2_ERST_MAX 4
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#define XHCI_HCSPARAMS2_MAX_SCRTCH_HI 21
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#define XHCI_HCSPARAMS2_SPR 26
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#define XHCI_HCSPARAMS2_MAX_SCRTCH_LO 27
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/* event types */
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#define XHCI_TRB_NORMAL 1
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#define XHCI_TRB_SETUP_STAGE 2
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#define XHCI_TRB_DATA_STAGE 3
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#define XHCI_TRB_STATUS_STAGE 4
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#define XHCI_TRB_ISOCH 5
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#define XHCI_TRB_LINK 6
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#define XHCI_TRB_EVENT_DATA 7
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#define XHCI_TRB_NOOP 8
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#define XHCI_TRB_SLOT_ENAB_CMD 9
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#define XHCI_TRB_SLOT_DISB_CMD 10
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#define XHCI_TRB_ADDR_DEV_CMD 11
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#define XHCI_TRB_CFG_ENDP_CMD 12
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#define XHCI_TRB_EVAL_CTX_CMD 13
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#define XHCI_TRB_RESET_ENDP_CMD 14
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#define XHCI_TRB_STOP_ENDP_CMD 15
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#define XHCI_TRB_SET_DRDQP_CMD 16
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#define XHCI_TRB_RESET_DEV_CMD 17
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#define XHCI_TRB_FORCE_EVT_CMD 18
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#define XHCI_TRB_NEGO_BANDW_CMD 19
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#define XHCI_TRB_SET_LTV_CMD 20
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#define XHCI_TRB_PORT_BANDW_CMD 21
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#define XHCI_TRB_FORCE_HEADER 22
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#define XHCI_TRB_NOOP_CMD 23
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#define XHCI_TRB_GET_EXTPRP_CMD 24
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#define XHCI_TRB_SET_EXTPRP_CMD 25
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#define XHCI_TRB_TRANSFER_EVENT 32
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#define XHCI_TRB_CMD_CMPL_EVENT 33
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#define XHCI_TRB_PORT_STS_CHNG 34
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#define XHCI_TRB_BANDW_RQ_EVENT 35
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#define XHCI_TRB_DOORBELL_EVENT 36
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#define XHCI_TRB_HOST_CTRL_EVNT 37
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#define XHCI_TRB_DEV_NOTIF_EVNT 38
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#define XHCI_TRB_MFINDEX_WRAP 39
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/* generic TRB bits */
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#define XHCI_GTRB_TRB_TYPE 10
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#define XHCI_GTRB_CYCLE_BIT 0
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/* command completion event TRB */
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#define XHCI_CCETRB_CTRL_SLOT_ID 24
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#define XHCI_CCETRB_CTRL_VFID 16
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#define XHCI_CCETRB_CTRL_TRB_TYPE 10
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#define XHCI_CCETRB_CTRL_CYCLEBIT 0
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#define XHCI_CCETRB_STS_CMPL_CODE 24
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/* transfer event TRB */
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#define XHCI_TETRB_CTRL_SLOT_ID 24
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#define XHCI_TETRB_CTRL_ENDPOINT 16
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#define XHCI_TETRB_CTRL_TRB_TYPE 10
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#define XHCI_TETRB_CTRL_EVT_DATA 2
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#define XHCI_TETRB_CTRL_CYCLEBIT 0
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#define XHCI_TETRB_STS_CMPL_CODE 24
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/* port status change event TRB */
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#define XHCI_PSCETRB_CTRL_TRB_TYPE 10
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#define XHCI_PSCETRB_CTRL_CYCLEBIT 0
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#define XHCI_PSCETRB_STS_CMPL_CODE 24
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#define XHCI_PSCETRB_PARAM_PORT_ID 24
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/* link TRB */
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#define XHCI_LNKTRB_CTRL_TRB_TYPE 10
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#define XHCI_LNKTRB_CTRL_IOC 5
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#define XHCI_LNKTRB_CTRL_CH 4
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#define XHCI_LNKTRB_CTRL_TC 1
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#define XHCI_LNKTRB_CTRL_CYCLEBIT 0
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#define XHCI_LNKTRB_STS_INTR_TRGT 22
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/* setup stage TRB */
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#define XHCI_SSTRB_CTRL_TRT 16
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#define XHCI_SSTRB_CTRL_TRB_TYPE 10
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#define XHCI_SSTRB_CTRL_IDT 6
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#define XHCI_SSTRB_CTRL_IOC 5
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#define XHCI_SSTRB_CTRL_CYCLEBIT 0
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#define XHCI_SSTRB_STS_INTR_TRGT 22
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#define XHCI_SSTRB_PARAM_WLENGTH 48
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#define XHCI_SSTRB_PARAM_WINDEX 32
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#define XHCI_SSTRB_PARAM_WVALUE 16
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#define XHCI_SSTRB_PARAM_BREQUEST 8
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#define XHCI_SSTRB_PARAM_BMREQUEST_TYPE 0
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/* setup stage TRB transfer types */
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#define XHCI_SSTRB_TRT_NO_DATA_STAGE 0
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#define XHCI_SSTRB_TRT_OUT_DATA_STAGE 2
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#define XHCI_SSTRB_TRT_IN_DATA_STAGE 3
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/* data stage TRB */
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#define XHCI_DSTRB_CTRL_DIR 16
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#define XHCI_DSTRB_CTRL_TRB_TYPE 10
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#define XHCI_DSTRB_CTRL_IDT 6
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#define XHCI_DSTRB_CTRL_IOC 5
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#define XHCI_DSTRB_CTRL_CH 4
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#define XHCI_DSTRB_CTRL_NS 3
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#define XHCI_DSTRB_CTRL_ISP 2
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#define XHCI_DSTRB_CTRL_ENT 1
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#define XHCI_DSTRB_CTRL_CYCLEBIT 0
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#define XHCI_DSTRB_STS_INTR_TRGT 22
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#define XHCI_DSTRB_STS_TD_SIZE 17
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/* status stage TRB */
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#define XHCI_STSTRB_CTRL_DIR 16
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#define XHCI_STSTRB_CTRL_TRB_TYPE 10
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#define XHCI_STSTRB_CTRL_IOC 5
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#define XHCI_STSTRB_CTRL_CH 4
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#define XHCI_STSTRB_CTRL_ENT 1
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#define XHCI_STSTRB_CTRL_CYCLEBIT 0
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#define XHCI_STSTRB_STS_INTR_TRGT 22
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/* extended capabilities */
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#define XHCI_EXTCAP_USB_LEGACY_SUPPORT 1
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#define XHCI_EXTCAP_SUPPORTED_PROTOCOL 2
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#define XHCI_EXTCAP_EXT_POWER_MNGMNT 3
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#define XHCI_EXTCAP_IO_VIRT 4
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#define XHCI_EXTCAP_MSG_INTR 5
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#define XHCI_EXTCAP_LOCAL_MEMORY 6
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#define XHCI_EXTCAP_USB_DEBUG 7
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#define XHCI_EXTCAP_EXT_MSG_INTR 8
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#define XHCI_EXTCAP_VENDOR_DEFINED 9
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/* PORTSC bits */
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#define XHCI_PORTSC_CCS 0
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#define XHCI_PORTSC_PED 1
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#define XHCI_PORTSC_OCA 3
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#define XHCI_PORTSC_PR 4
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#define XHCI_PORTSC_PLS 5
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#define XHCI_PORTSC_PP 9
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#define XHCI_PORTSC_PORTSPEED 10
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#define XHCI_PORTSC_PIC 14
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#define XHCI_PORTSC_LWS 16
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#define XHCI_PORTSC_CSC 17
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#define XHCI_PORTSC_PEC 18
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#define XHCI_PORTSC_WRC 19
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#define XHCI_PORTSC_OCC 20
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#define XHCI_PORTSC_PRC 21
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#define XHCI_PORTSC_PLC 22
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#define XHCI_PORTSC_CEC 23
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#define XHCI_PORTSC_CAS 24
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#define XHCI_PORTSC_WCE 25
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#define XCHI_PORTSC_WDE 26
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#define XHCI_PORTSC_WOE 27
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#define XHCI_PORTSC_DR 30
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#define XHCI_PORTSC_WPR 31
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/* endpoint context */
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#define XHCI_EPCTX_EP_STATE 0
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#define XHCI_EPCTX_MULT 8
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#define XHCI_EPCTX_MAXPSTRAMS 10
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#define XHCI_EPCTX_LSA 15
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#define XHCI_EPCTX_INTERVAL 16
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#define XHCI_EPCTX_MAX_ESIT_HI 24
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#define XHCI_EPCTX_ERR_COUNT 1
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#define XHCI_EPCTX_EP_TYPE 3
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#define XHCI_EPCTX_HID 7
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#define XHCI_EPCTX_MAX_BURST_SZ 8
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#define XHCI_EPCTX_MAX_PKT_SZ 16
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#define XHCI_EPCTX_DCS 0
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#define XHCI_EPCTX_TR_DQ_PTR 4
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#define XHCI_EPCTX_AVG_TRB_LEN 0
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#define XHCI_EPCTX_MAX_ESIT_LOW 16
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/* endpoint types */
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#define XHCI_EP_INVALID 0
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#define XHCI_EP_ISOCH_OUT 1
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#define XHCI_EP_BULK_OUT 2
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#define XHCI_EP_INTR_OUT 3
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#define XHCI_EP_CTRL_BI 4
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#define XHCI_EP_ISOCH_IN 5
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#define XHCI_EP_BULK_IN 6
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#define XHCI_EP_INTR_IN 7
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/* slot context */
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#define XHIC_SLCTX_ROUTE_STR 0
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#define XHCI_SLCTX_SPEED 20
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#define XHCI_SLCTX_MTT 25
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#define XHCI_SLCTX_HUB 26
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#define XHCI_SLCTX_CTX_ENTRIES 27
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#define XHCI_SLCTX_MAXEXITLTNCY 0
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#define XHCI_SLCTX_ROOTHUBPRNUM 16
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#define XHCI_SLCTX_PORT_COUNT 24
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#define XHCI_SLCTX_PRNT_HUB_SLT 0
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#define XHCI_SLCTX_PARENT_PORT 8
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#define XHCI_SLCTX_TT_THINKTIME 16
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#define XHCI_SLCTX_INTR_TARGET 22
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#define XHCI_SLCTX_USB_DEV_ADDR 0
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#define XHCI_SLCTX_SLOT_STATE 27
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/* clang-format on */
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static uint8_t xhci_get_device_ctx_idx (struct usb_endpoint_desc* endpoint);
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static void xhci_write8 (uintptr_t base, uint32_t reg, uint8_t value) {
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*(volatile uint8_t*)(base + reg) = value;
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}
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static void xhci_write16 (uintptr_t base, uint32_t reg, uint16_t value) {
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*(volatile uint16_t*)(base + reg) = value;
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}
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static void xhci_write32 (uintptr_t base, uint32_t reg, uint32_t value) {
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*(volatile uint32_t*)(base + reg) = value;
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}
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@@ -314,10 +33,6 @@ static uint8_t xhci_read8 (uintptr_t base, uint32_t reg) {
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return *(volatile uint8_t*)(base + reg);
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}
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static uint16_t xhci_read16 (uintptr_t base, uint32_t reg) {
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return *(volatile uint16_t*)(base + reg);
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}
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static uint32_t xhci_read32 (uintptr_t base, uint32_t reg) {
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return *(volatile uint32_t*)(base + reg);
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}
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@@ -347,12 +62,15 @@ static void xhci_create_usb_device (struct xhci* xhci, struct xhci_port* xhci_po
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list_append (xhci->xhci_usb_devices, &usb_device->usb_devices_link);
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}
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static void xhci_delete_usb_device (struct xhci* xhci, struct xhci_port* xhci_port) {
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struct xhci_usb_device* usb_device;
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static void xhci_delete_usb_device (struct xhci* xhci, struct xhci_port* xhci_port,
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struct proc* proc, struct reschedule_ctx* rctx) {
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struct xhci_usb_device* usb_device = NULL;
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list_find (struct xhci_usb_device, xhci->xhci_usb_devices, usb_device, xhci_port->port_value,
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xhci_port->port_value, usb_devices_link);
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device_delete (usb_device->device->key, proc, rctx);
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list_remove (xhci->xhci_usb_devices, &usb_device->usb_devices_link);
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if (usb_device->endpoint0_ring.phys != 0)
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@@ -1186,20 +904,24 @@ static bool xhci_usb_device_setup_get_config_full (struct xhci* xhci,
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static void xhci_poll_setup_init_ifs (struct xhci* xhci, struct xhci_usb_device* usb_device,
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uint64_t* lockflags) {
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struct reschedule_ctx rctx;
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memset (&rctx, 0, sizeof (rctx));
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for (size_t if0 = 0; if0 < usb_device->ifs_count; if0++) {
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struct xhci_usb_device_if* if_ = &usb_device->ifs[if0];
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for (size_t i = 0; i < USB_DRIVER_MAX_MATCHES; i++) {
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struct usb_driver_info* info = &usb_driver_infos[i];
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DEBUG ("%u %u / %u %u / %u %u\n", if_->desc.if_class, info->if_class, if_->desc.if_subclass,
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info->if_subclass, if_->desc.if_proto, info->if_proto);
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if (if_->desc.if_class == info->if_class &&
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if_->desc.if_subclass == info->if_subclass &&
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if_->desc.if_proto == info->if_proto) {
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if (!info->init ())
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struct device* device = info->init (xhci, usb_device, thiscpu->kproc, &rctx, lockflags);
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if (device == NULL)
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DEBUG ("USB driver failed to initialize. Skipping device!\n");
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usb_device->device = device;
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}
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}
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}
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@@ -1227,7 +949,8 @@ static void xhci_poll_setup_devices (struct xhci* xhci, uint64_t* lockflags) {
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}
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}
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static void xhci_poll_port_changes (struct xhci* xhci) {
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static void xhci_poll_port_changes (struct xhci* xhci, struct proc* proc,
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struct reschedule_ctx* rctx) {
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struct list_node_link *port_change_link, *tmp_port_change_link;
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struct xhci_port* xhci_port;
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@@ -1248,7 +971,7 @@ static void xhci_poll_port_changes (struct xhci* xhci) {
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} else {
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DEBUG ("Device detached from port %u!\n", change->port);
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xhci_delete_usb_device (xhci, xhci_port);
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xhci_delete_usb_device (xhci, xhci_port, proc, rctx);
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}
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}
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@@ -1256,10 +979,83 @@ static void xhci_poll_port_changes (struct xhci* xhci) {
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}
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}
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int xhci_bulk_transfer (struct xhci* xhci, struct xhci_usb_device* usb_device,
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uint8_t endpoint_addr, uintptr_t buffer_phys, size_t buffer_size,
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uint64_t* lockflags) {
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struct xhci_usb_device_endpoint* endpoint = NULL;
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for (size_t ep = 0; ep < XHCI_USB_DEVICE_ENDPOINTS_MAX; ep++) {
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||||
endpoint = &usb_device->endpoints[ep];
|
||||
|
||||
if (endpoint->desc.endpoint_addr == endpoint_addr)
|
||||
break;
|
||||
}
|
||||
|
||||
if (endpoint == NULL)
|
||||
return -ST_NOT_FOUND;
|
||||
|
||||
/* not bulk */
|
||||
if ((endpoint->desc.attrs & 0x03) != 0x02)
|
||||
return -ST_NOT_FOUND;
|
||||
|
||||
if (usb_device->slot_id < 0)
|
||||
return -ST_NOT_FOUND;
|
||||
|
||||
xhci->last_cmpl_code = 0;
|
||||
atomic_store (&xhci->pending, true);
|
||||
|
||||
uint32_t rem = buffer_size;
|
||||
uint32_t current = buffer_phys;
|
||||
|
||||
while (rem > 0) {
|
||||
uint32_t chunk = rem > 0x1FFFFU ? 0x1FFFFU : rem;
|
||||
|
||||
struct xhci_trb trb;
|
||||
memset (&trb, 0, sizeof (trb));
|
||||
trb.param = current;
|
||||
trb.status = chunk;
|
||||
|
||||
write_memory_barrier ();
|
||||
|
||||
trb.ctrl = (XHCI_TRB_NORMAL << XHCI_GTRB_TRB_TYPE);
|
||||
|
||||
if (rem != chunk) {
|
||||
trb.ctrl |= (1 << XHCI_DSTRB_CTRL_CH);
|
||||
} else {
|
||||
trb.ctrl |= (1 << XHCI_DSTRB_CTRL_IOC) | (1 << XHCI_DSTRB_CTRL_ISP);
|
||||
}
|
||||
|
||||
xhci_ring_put_trb (&endpoint->transfer_ring, trb);
|
||||
|
||||
current += chunk;
|
||||
rem -= chunk;
|
||||
}
|
||||
|
||||
uint32_t dci = xhci_get_device_ctx_idx (&endpoint->desc);
|
||||
|
||||
int timeout = 100;
|
||||
|
||||
spin_unlock (&xhci->device->lock, *lockflags);
|
||||
|
||||
xhci_write32 (xhci->xhci_doorbell_base, usb_device->slot_id * 4, dci);
|
||||
|
||||
while (atomic_load (&xhci->pending) && --timeout > 0)
|
||||
stall_ms (10);
|
||||
|
||||
spin_lock (&xhci->device->lock, lockflags);
|
||||
|
||||
if (timeout == 0) {
|
||||
DEBUG ("bulk transfer timed out\n");
|
||||
return -ST_TRY_AGAIN;
|
||||
}
|
||||
|
||||
return xhci->last_cmpl_code == 1 ? ST_OK : -ST_USB_CTRL_ERROR;
|
||||
}
|
||||
|
||||
DEFINE_DEVICE_OP (xhci_poll_driver) {
|
||||
struct xhci* xhci = device->udata;
|
||||
|
||||
xhci_poll_port_changes (xhci);
|
||||
xhci_poll_port_changes (xhci, proc, rctx);
|
||||
xhci_poll_setup_devices (xhci, lockflags);
|
||||
|
||||
return ST_OK;
|
||||
@@ -1436,7 +1232,7 @@ DEFINE_DEVICE_FINI (xhci_fini) {
|
||||
|
||||
list_remove (xhci->xhci_ports, &port->ports_link);
|
||||
|
||||
xhci_delete_usb_device (xhci, port);
|
||||
xhci_delete_usb_device (xhci, port, proc, rctx);
|
||||
free (port);
|
||||
}
|
||||
|
||||
|
||||
Reference in New Issue
Block a user